1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <nand.h> 18 #include <netdev.h> 19 #include <miiphy.h> 20 #include <spi.h> 21 #include <asm/io.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/soc.h> 24 #include <asm/arch/mpp.h> 25 26 #include "../common/common.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * BOCO FPGA definitions 32 */ 33 #define BOCO 0x10 34 #define REG_CTRL_H 0x02 35 #define MASK_WRL_UNITRUN 0x01 36 #define MASK_RBX_PGY_PRESENT 0x40 37 #define REG_IRQ_CIRQ2 0x2d 38 #define MASK_RBI_DEFECT_16 0x01 39 40 /* 41 * PHY registers definitions 42 */ 43 #define PHY_MARVELL_OUI 0x5043 44 #define PHY_MARVELL_88E1118_MODEL 0x0022 45 #define PHY_MARVELL_88E1118R_MODEL 0x0024 46 47 #define PHY_MARVELL_PAGE_REG 0x0016 48 #define PHY_MARVELL_DEFAULT_PAGE 0x0000 49 50 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003 51 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010 52 53 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000 54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0) 55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4) 56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8) 57 58 /* I/O pin to erase flash RGPP09 = MPP43 */ 59 #define KM_FLASH_ERASE_ENABLE 43 60 61 /* Multi-Purpose Pins Functionality configuration */ 62 static const u32 kwmpp_config[] = { 63 MPP0_NF_IO2, 64 MPP1_NF_IO3, 65 MPP2_NF_IO4, 66 MPP3_NF_IO5, 67 MPP4_NF_IO6, 68 MPP5_NF_IO7, 69 MPP6_SYSRST_OUTn, 70 #if defined(KM_PCIE_RESET_MPP7) 71 MPP7_GPO, 72 #else 73 MPP7_PEX_RST_OUTn, 74 #endif 75 #if defined(CONFIG_SYS_I2C_SOFT) 76 MPP8_GPIO, /* SDA */ 77 MPP9_GPIO, /* SCL */ 78 #endif 79 MPP10_UART0_TXD, 80 MPP11_UART0_RXD, 81 MPP12_GPO, /* Reserved */ 82 MPP13_UART1_TXD, 83 MPP14_UART1_RXD, 84 MPP15_GPIO, /* Not used */ 85 MPP16_GPIO, /* Not used */ 86 MPP17_GPIO, /* Reserved */ 87 MPP18_NF_IO0, 88 MPP19_NF_IO1, 89 MPP20_GPIO, 90 MPP21_GPIO, 91 MPP22_GPIO, 92 MPP23_GPIO, 93 MPP24_GPIO, 94 MPP25_GPIO, 95 MPP26_GPIO, 96 MPP27_GPIO, 97 MPP28_GPIO, 98 MPP29_GPIO, 99 MPP30_GPIO, 100 MPP31_GPIO, 101 MPP32_GPIO, 102 MPP33_GPIO, 103 MPP34_GPIO, /* CDL1 (input) */ 104 MPP35_GPIO, /* CDL2 (input) */ 105 MPP36_GPIO, /* MAIN_IRQ (input) */ 106 MPP37_GPIO, /* BOARD_LED */ 107 MPP38_GPIO, /* Piggy3 LED[1] */ 108 MPP39_GPIO, /* Piggy3 LED[2] */ 109 MPP40_GPIO, /* Piggy3 LED[3] */ 110 MPP41_GPIO, /* Piggy3 LED[4] */ 111 MPP42_GPIO, /* Piggy3 LED[5] */ 112 MPP43_GPIO, /* Piggy3 LED[6] */ 113 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 114 MPP45_GPIO, /* Piggy3 LED[8] */ 115 MPP46_GPIO, /* Reserved */ 116 MPP47_GPIO, /* Reserved */ 117 MPP48_GPIO, /* Reserved */ 118 MPP49_GPIO, /* SW_INTOUTn */ 119 0 120 }; 121 122 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; 123 124 #if defined(CONFIG_KM_MGCOGE3UN) 125 /* 126 * Wait for startup OK from mgcoge3ne 127 */ 128 static int startup_allowed(void) 129 { 130 unsigned char buf; 131 132 /* 133 * Read CIRQ16 bit (bit 0) 134 */ 135 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 136 printf("%s: Error reading Boco\n", __func__); 137 else 138 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 139 return 1; 140 return 0; 141 } 142 #endif 143 144 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 145 /* 146 * All boards with PIGGY4 connected via a simple switch have ethernet always 147 * present. 148 */ 149 int ethernet_present(void) 150 { 151 return 1; 152 } 153 #else 154 int ethernet_present(void) 155 { 156 uchar buf; 157 int ret = 0; 158 159 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 160 printf("%s: Error reading Boco\n", __func__); 161 return -1; 162 } 163 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 164 ret = 1; 165 166 return ret; 167 } 168 #endif 169 170 static int initialize_unit_leds(void) 171 { 172 /* 173 * Init the unit LEDs per default they all are 174 * ok apart from bootstat 175 */ 176 uchar buf; 177 178 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 179 printf("%s: Error reading Boco\n", __func__); 180 return -1; 181 } 182 buf |= MASK_WRL_UNITRUN; 183 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 184 printf("%s: Error writing Boco\n", __func__); 185 return -1; 186 } 187 return 0; 188 } 189 190 static void set_bootcount_addr(void) 191 { 192 uchar buf[32]; 193 unsigned int bootcountaddr; 194 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 195 sprintf((char *)buf, "0x%x", bootcountaddr); 196 env_set("bootcountaddr", (char *)buf); 197 } 198 199 int misc_init_r(void) 200 { 201 #if defined(CONFIG_KM_MGCOGE3UN) 202 char *wait_for_ne; 203 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 204 wait_for_ne = env_get("waitforne"); 205 206 if ((wait_for_ne != NULL) && (dip_switch == 0)) { 207 if (strcmp(wait_for_ne, "true") == 0) { 208 int cnt = 0; 209 int abort = 0; 210 puts("NE go: "); 211 while (startup_allowed() == 0) { 212 if (tstc()) { 213 (void) getc(); /* consume input */ 214 abort = 1; 215 break; 216 } 217 udelay(200000); 218 cnt++; 219 if (cnt == 5) 220 puts("wait\b\b\b\b"); 221 if (cnt == 10) { 222 cnt = 0; 223 puts(" \b\b\b\b"); 224 } 225 } 226 if (abort == 1) 227 printf("\nAbort waiting for ne\n"); 228 else 229 puts("OK\n"); 230 } 231 } 232 #endif 233 234 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 235 236 initialize_unit_leds(); 237 set_km_env(); 238 set_bootcount_addr(); 239 return 0; 240 } 241 242 int board_early_init_f(void) 243 { 244 #if defined(CONFIG_SYS_I2C_SOFT) 245 u32 tmp; 246 247 /* set the 2 bitbang i2c pins as output gpios */ 248 tmp = readl(MVEBU_GPIO0_BASE + 4); 249 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); 250 #endif 251 /* adjust SDRAM size for bank 0 */ 252 mvebu_sdram_size_adjust(0); 253 kirkwood_mpp_conf(kwmpp_config, NULL); 254 return 0; 255 } 256 257 int board_init(void) 258 { 259 /* address of boot parameters */ 260 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 261 262 /* 263 * The KM_FLASH_GPIO_PIN switches between using a 264 * NAND or a SPI FLASH. Set this pin on start 265 * to NAND mode. 266 */ 267 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 268 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 269 270 #if defined(CONFIG_SYS_I2C_SOFT) 271 /* 272 * Reinit the GPIO for I2C Bitbang driver so that the now 273 * available gpio framework is consistent. The calls to 274 * direction output in are not necessary, they are already done in 275 * board_early_init_f 276 */ 277 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 278 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 279 #endif 280 281 #if defined(CONFIG_SYS_EEPROM_WREN) 282 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 283 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 284 #endif 285 286 #if defined(CONFIG_KM_FPGA_CONFIG) 287 trigger_fpga_config(); 288 #endif 289 290 return 0; 291 } 292 293 int board_late_init(void) 294 { 295 #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN)) 296 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 297 298 /* if pin 1 do full erase */ 299 if (dip_switch != 0) { 300 /* start bootloader */ 301 puts("DIP: Enabled\n"); 302 env_set("actual_bank", "0"); 303 } 304 #endif 305 306 #if defined(CONFIG_KM_FPGA_CONFIG) 307 wait_for_fpga_config(); 308 fpga_reset(); 309 toggle_eeprom_spi_bus(); 310 #endif 311 return 0; 312 } 313 314 int board_spi_claim_bus(struct spi_slave *slave) 315 { 316 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 317 318 return 0; 319 } 320 321 void board_spi_release_bus(struct spi_slave *slave) 322 { 323 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 324 } 325 326 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 327 328 #define PHY_LED_SEL_REG 0x18 329 #define PHY_LED0_LINK (0x5) 330 #define PHY_LED1_ACT (0x8<<4) 331 #define PHY_LED2_INT (0xe<<8) 332 #define PHY_SPEC_CTRL_REG 0x1c 333 #define PHY_RGMII_CLK_STABLE (0x1<<10) 334 #define PHY_CLSA (0x1<<1) 335 336 /* Configure and enable MV88E3018 PHY */ 337 void reset_phy(void) 338 { 339 char *name = "egiga0"; 340 unsigned short reg; 341 342 if (miiphy_set_current_dev(name)) 343 return; 344 345 /* RGMII clk transition on data stable */ 346 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 347 printf("Error reading PHY spec ctrl reg\n"); 348 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 349 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 350 printf("Error writing PHY spec ctrl reg\n"); 351 352 /* leds setup */ 353 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 354 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 355 printf("Error writing PHY LED reg\n"); 356 357 /* reset the phy */ 358 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 359 } 360 #elif defined(CONFIG_KM_PIGGY4_88E6352) 361 362 #include <mv88e6352.h> 363 364 #if defined(CONFIG_KM_NUSA) 365 struct mv88e_sw_reg extsw_conf[] = { 366 /* 367 * port 0, PIGGY4, autoneg 368 * first the fix for the 1000Mbits Autoneg, this is from 369 * a Marvell errata, the regs are undocumented 370 */ 371 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 372 { PHY(0), PHY_STATUS, AN1000FIX }, 373 { PHY(0), PHY_PAGE, 0 }, 374 /* now the real port and phy configuration */ 375 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 376 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 377 { PHY(0), PHY_1000_CTRL, NO_ADV }, 378 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 379 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 380 FULL_DUPLEX }, 381 /* port 1, unused */ 382 { PORT(1), PORT_CTRL, PORT_DIS }, 383 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 384 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 385 /* port 2, unused */ 386 { PORT(2), PORT_CTRL, PORT_DIS }, 387 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 388 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 389 /* port 3, unused */ 390 { PORT(3), PORT_CTRL, PORT_DIS }, 391 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 392 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 393 /* port 4, ICNEV, SerDes, SGMII */ 394 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 395 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 396 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 397 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 398 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 399 /* port 5, CPU_RGMII */ 400 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 401 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 402 FULL_DPX_FOR | SPEED_1000_FOR }, 403 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 404 /* port 6, unused, this port has no phy */ 405 { PORT(6), PORT_CTRL, PORT_DIS }, 406 }; 407 #else 408 struct mv88e_sw_reg extsw_conf[] = {}; 409 #endif 410 411 void reset_phy(void) 412 { 413 #if defined(CONFIG_KM_MVEXTSW_ADDR) 414 char *name = "egiga0"; 415 416 if (miiphy_set_current_dev(name)) 417 return; 418 419 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 420 ARRAY_SIZE(extsw_conf)); 421 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 422 #endif 423 } 424 425 #else 426 /* Configure and enable MV88E1118 PHY on the piggy*/ 427 void reset_phy(void) 428 { 429 unsigned int oui; 430 unsigned char model, rev; 431 432 char *name = "egiga0"; 433 434 if (miiphy_set_current_dev(name)) 435 return; 436 437 /* reset the phy */ 438 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 439 440 /* get PHY model */ 441 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev)) 442 return; 443 444 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */ 445 if ((oui == PHY_MARVELL_OUI) && 446 (model == PHY_MARVELL_88E1118R_MODEL)) { 447 /* set page register to 3 */ 448 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 449 PHY_MARVELL_PAGE_REG, 450 PHY_MARVELL_88E1118R_LED_CTRL_PAGE)) 451 printf("Error writing PHY page reg\n"); 452 453 /* 454 * leds setup as printed on PCB: 455 * LED2 (Link): 0x0 (On Link, Off No Link) 456 * LED1 (Activity): 0x3 (On Activity, Off No Activity) 457 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else) 458 */ 459 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 460 PHY_MARVELL_88E1118R_LED_CTRL_REG, 461 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED | 462 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB | 463 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT | 464 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK)) 465 printf("Error writing PHY LED reg\n"); 466 467 /* set page register back to 0 */ 468 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 469 PHY_MARVELL_PAGE_REG, 470 PHY_MARVELL_DEFAULT_PAGE)) 471 printf("Error writing PHY page reg\n"); 472 } 473 } 474 #endif 475 476 477 #if defined(CONFIG_HUSH_INIT_VAR) 478 int hush_init_var(void) 479 { 480 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 481 return 0; 482 } 483 #endif 484 485 #if defined(CONFIG_SYS_I2C_SOFT) 486 void set_sda(int state) 487 { 488 I2C_ACTIVE; 489 I2C_SDA(state); 490 } 491 492 void set_scl(int state) 493 { 494 I2C_SCL(state); 495 } 496 497 int get_sda(void) 498 { 499 I2C_TRISTATE; 500 return I2C_READ; 501 } 502 503 int get_scl(void) 504 { 505 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 506 } 507 #endif 508 509 #if defined(CONFIG_POST) 510 511 #define KM_POST_EN_L 44 512 #define POST_WORD_OFF 8 513 514 int post_hotkeys_pressed(void) 515 { 516 #if defined(CONFIG_KM_COGE5UN) 517 return kw_gpio_get_value(KM_POST_EN_L); 518 #else 519 return !kw_gpio_get_value(KM_POST_EN_L); 520 #endif 521 } 522 523 ulong post_word_load(void) 524 { 525 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 526 return in_le32(addr); 527 528 } 529 void post_word_store(ulong value) 530 { 531 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 532 out_le32(addr, value); 533 } 534 535 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 536 { 537 *vstart = CONFIG_SYS_SDRAM_BASE; 538 539 /* we go up to relocation plus a 1 MB margin */ 540 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 541 542 return 0; 543 } 544 #endif 545 546 #if defined(CONFIG_SYS_EEPROM_WREN) 547 int eeprom_write_enable(unsigned dev_addr, int state) 548 { 549 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 550 551 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 552 } 553 #endif 554