1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <i2c.h> 33 #include <nand.h> 34 #include <netdev.h> 35 #include <miiphy.h> 36 #include <asm/io.h> 37 #include <asm/arch/kirkwood.h> 38 #include <asm/arch/mpp.h> 39 40 #include "../common/common.h" 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* Multi-Purpose Pins Functionality configuration */ 45 u32 kwmpp_config[] = { 46 MPP0_NF_IO2, 47 MPP1_NF_IO3, 48 MPP2_NF_IO4, 49 MPP3_NF_IO5, 50 MPP4_NF_IO6, 51 MPP5_NF_IO7, 52 MPP6_SYSRST_OUTn, 53 MPP7_PEX_RST_OUTn, 54 #if defined(CONFIG_SOFT_I2C) 55 MPP8_GPIO, /* SDA */ 56 MPP9_GPIO, /* SCL */ 57 #endif 58 #if defined(CONFIG_HARD_I2C) 59 MPP8_TW_SDA, 60 MPP9_TW_SCK, 61 #endif 62 MPP10_UART0_TXD, 63 MPP11_UART0_RXD, 64 MPP12_GPO, /* Reserved */ 65 MPP13_UART1_TXD, 66 MPP14_UART1_RXD, 67 MPP15_GPIO, /* Not used */ 68 MPP16_GPIO, /* Not used */ 69 MPP17_GPIO, /* Reserved */ 70 MPP18_NF_IO0, 71 MPP19_NF_IO1, 72 MPP20_GPIO, 73 MPP21_GPIO, 74 MPP22_GPIO, 75 MPP23_GPIO, 76 MPP24_GPIO, 77 MPP25_GPIO, 78 MPP26_GPIO, 79 MPP27_GPIO, 80 MPP28_GPIO, 81 MPP29_GPIO, 82 MPP30_GPIO, 83 MPP31_GPIO, 84 MPP32_GPIO, 85 MPP33_GPIO, 86 MPP34_GPIO, /* CDL1 (input) */ 87 MPP35_GPIO, /* CDL2 (input) */ 88 MPP36_GPIO, /* MAIN_IRQ (input) */ 89 MPP37_GPIO, /* BOARD_LED */ 90 MPP38_GPIO, /* Piggy3 LED[1] */ 91 MPP39_GPIO, /* Piggy3 LED[2] */ 92 MPP40_GPIO, /* Piggy3 LED[3] */ 93 MPP41_GPIO, /* Piggy3 LED[4] */ 94 MPP42_GPIO, /* Piggy3 LED[5] */ 95 MPP43_GPIO, /* Piggy3 LED[6] */ 96 MPP44_GPIO, /* Piggy3 LED[7] */ 97 MPP45_GPIO, /* Piggy3 LED[8] */ 98 MPP46_GPIO, /* Reserved */ 99 MPP47_GPIO, /* Reserved */ 100 MPP48_GPIO, /* Reserved */ 101 MPP49_GPIO, /* SW_INTOUTn */ 102 0 103 }; 104 105 int ethernet_present(void) 106 { 107 uchar buf; 108 int ret = 0; 109 110 if (i2c_read(0x10, 2, 1, &buf, 1) != 0) { 111 printf ("%s: Error reading Boco\n", __FUNCTION__); 112 return -1; 113 } 114 if ((buf & 0x40) == 0x40) { 115 ret = 1; 116 } 117 return ret; 118 } 119 120 int misc_init_r(void) 121 { 122 char *str; 123 int mach_type; 124 125 puts("Piggy:"); 126 if (ethernet_present() == 0) 127 puts (" not"); 128 puts(" present\n"); 129 130 str = getenv("mach_type"); 131 if (str != NULL) { 132 mach_type = simple_strtoul(str, NULL, 10); 133 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); 134 gd->bd->bi_arch_number = mach_type; 135 } 136 return 0; 137 } 138 139 int board_early_init_f(void) 140 { 141 u32 tmp; 142 143 kirkwood_mpp_conf(kwmpp_config); 144 145 /* 146 * The FLASH_GPIO_PIN switches between using a 147 * NAND or a SPI FLASH. Set this pin on start 148 * to NAND mode. 149 */ 150 tmp = readl(KW_GPIO0_BASE); 151 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 152 tmp = readl(KW_GPIO0_BASE + 4); 153 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); 154 printf("KM: setting NAND mode\n"); 155 156 #if defined(CONFIG_SOFT_I2C) 157 /* init the GPIO for I2C Bitbang driver */ 158 kw_gpio_set_valid(SUEN3_SDA_PIN, 1); 159 kw_gpio_set_valid(SUEN3_SCL_PIN, 1); 160 kw_gpio_direction_output(SUEN3_SDA_PIN, 0); 161 kw_gpio_direction_output(SUEN3_SCL_PIN, 0); 162 #endif 163 #if defined(CONFIG_SYS_EEPROM_WREN) 164 kw_gpio_set_valid(SUEN3_ENV_WP, 38); 165 kw_gpio_direction_output(SUEN3_ENV_WP, 1); 166 #endif 167 168 return 0; 169 } 170 171 int board_init(void) 172 { 173 /* 174 * arch number of board 175 */ 176 gd->bd->bi_arch_number = MACH_TYPE_SUEN3; 177 178 /* address of boot parameters */ 179 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 180 181 return 0; 182 } 183 184 #if defined(CONFIG_CMD_SF) 185 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 186 { 187 u32 tmp; 188 if (argc < 2) 189 return cmd_usage(cmdtp); 190 191 if ((strcmp(argv[1], "off") == 0)) { 192 printf("SPI FLASH disabled, NAND enabled\n"); 193 /* Multi-Purpose Pins Functionality configuration */ 194 kwmpp_config[0] = MPP0_NF_IO2; 195 kwmpp_config[1] = MPP1_NF_IO3; 196 kwmpp_config[2] = MPP2_NF_IO4; 197 kwmpp_config[3] = MPP3_NF_IO5; 198 199 kirkwood_mpp_conf(kwmpp_config); 200 tmp = readl(KW_GPIO0_BASE); 201 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 202 } else if ((strcmp(argv[1], "on") == 0)) { 203 printf("SPI FLASH enabled, NAND disabled\n"); 204 /* Multi-Purpose Pins Functionality configuration */ 205 kwmpp_config[0] = MPP0_SPI_SCn; 206 kwmpp_config[1] = MPP1_SPI_MOSI; 207 kwmpp_config[2] = MPP2_SPI_SCK; 208 kwmpp_config[3] = MPP3_SPI_MISO; 209 210 kirkwood_mpp_conf(kwmpp_config); 211 tmp = readl(KW_GPIO0_BASE); 212 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); 213 } else { 214 return cmd_usage(cmdtp); 215 } 216 217 return 0; 218 } 219 220 U_BOOT_CMD( 221 spitoggle, 2, 0, do_spi_toggle, 222 "En-/disable SPI FLASH access", 223 "<on|off> - Enable (on) or disable (off) SPI FLASH access\n" 224 ); 225 #endif 226 227 int dram_init(void) 228 { 229 /* dram_init must store complete ramsize in gd->ram_size */ 230 /* Fix this */ 231 gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0), 232 kw_sdram_bs(0)); 233 return 0; 234 } 235 236 void dram_init_banksize(void) 237 { 238 int i; 239 240 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 241 gd->bd->bi_dram[i].start = kw_sdram_bar(i); 242 gd->bd->bi_dram[i].size = kw_sdram_bs(i); 243 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), 244 kw_sdram_bs(i)); 245 } 246 } 247 248 /* Configure and enable MV88E1118 PHY */ 249 void reset_phy(void) 250 { 251 char *name = "egiga0"; 252 253 if (miiphy_set_current_dev(name)) 254 return; 255 256 /* reset the phy */ 257 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 258 } 259 260 #if defined(CONFIG_HUSH_INIT_VAR) 261 int hush_init_var (void) 262 { 263 ivm_read_eeprom (); 264 return 0; 265 } 266 #endif 267 268 #if defined(CONFIG_BOOTCOUNT_LIMIT) 269 void bootcount_store (ulong a) 270 { 271 volatile ulong *save_addr; 272 volatile ulong size = 0; 273 int i; 274 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 275 size += gd->bd->bi_dram[i].size; 276 } 277 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 278 writel(a, save_addr); 279 writel(BOOTCOUNT_MAGIC, &save_addr[1]); 280 } 281 282 ulong bootcount_load (void) 283 { 284 volatile ulong *save_addr; 285 volatile ulong size = 0; 286 int i; 287 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 288 size += gd->bd->bi_dram[i].size; 289 } 290 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 291 if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC) 292 return 0; 293 else 294 return readl(save_addr); 295 } 296 #endif 297 298 #if defined(CONFIG_SOFT_I2C) 299 void set_sda (int state) 300 { 301 I2C_ACTIVE; 302 I2C_SDA(state); 303 } 304 305 void set_scl (int state) 306 { 307 I2C_SCL(state); 308 } 309 310 int get_sda (void) 311 { 312 I2C_TRISTATE; 313 return I2C_READ; 314 } 315 316 int get_scl (void) 317 { 318 return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0); 319 } 320 #endif 321 322 #if defined(CONFIG_SYS_EEPROM_WREN) 323 int eeprom_write_enable (unsigned dev_addr, int state) 324 { 325 kw_gpio_set_value(SUEN3_ENV_WP, !state); 326 327 return !kw_gpio_get_value(SUEN3_ENV_WP); 328 } 329 #endif 330