1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <nand.h> 18 #include <netdev.h> 19 #include <miiphy.h> 20 #include <spi.h> 21 #include <asm/io.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/soc.h> 24 #include <asm/arch/mpp.h> 25 26 #include "../common/common.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * BOCO FPGA definitions 32 */ 33 #define BOCO 0x10 34 #define REG_CTRL_H 0x02 35 #define MASK_WRL_UNITRUN 0x01 36 #define MASK_RBX_PGY_PRESENT 0x40 37 #define REG_IRQ_CIRQ2 0x2d 38 #define MASK_RBI_DEFECT_16 0x01 39 40 /* Multi-Purpose Pins Functionality configuration */ 41 static const u32 kwmpp_config[] = { 42 MPP0_NF_IO2, 43 MPP1_NF_IO3, 44 MPP2_NF_IO4, 45 MPP3_NF_IO5, 46 MPP4_NF_IO6, 47 MPP5_NF_IO7, 48 MPP6_SYSRST_OUTn, 49 #if defined(KM_PCIE_RESET_MPP7) 50 MPP7_GPO, 51 #else 52 MPP7_PEX_RST_OUTn, 53 #endif 54 #if defined(CONFIG_SYS_I2C_SOFT) 55 MPP8_GPIO, /* SDA */ 56 MPP9_GPIO, /* SCL */ 57 #endif 58 #if defined(CONFIG_HARD_I2C) 59 MPP8_TW_SDA, 60 MPP9_TW_SCK, 61 #endif 62 MPP10_UART0_TXD, 63 MPP11_UART0_RXD, 64 MPP12_GPO, /* Reserved */ 65 MPP13_UART1_TXD, 66 MPP14_UART1_RXD, 67 MPP15_GPIO, /* Not used */ 68 MPP16_GPIO, /* Not used */ 69 MPP17_GPIO, /* Reserved */ 70 MPP18_NF_IO0, 71 MPP19_NF_IO1, 72 MPP20_GPIO, 73 MPP21_GPIO, 74 MPP22_GPIO, 75 MPP23_GPIO, 76 MPP24_GPIO, 77 MPP25_GPIO, 78 MPP26_GPIO, 79 MPP27_GPIO, 80 MPP28_GPIO, 81 MPP29_GPIO, 82 MPP30_GPIO, 83 MPP31_GPIO, 84 MPP32_GPIO, 85 MPP33_GPIO, 86 MPP34_GPIO, /* CDL1 (input) */ 87 MPP35_GPIO, /* CDL2 (input) */ 88 MPP36_GPIO, /* MAIN_IRQ (input) */ 89 MPP37_GPIO, /* BOARD_LED */ 90 MPP38_GPIO, /* Piggy3 LED[1] */ 91 MPP39_GPIO, /* Piggy3 LED[2] */ 92 MPP40_GPIO, /* Piggy3 LED[3] */ 93 MPP41_GPIO, /* Piggy3 LED[4] */ 94 MPP42_GPIO, /* Piggy3 LED[5] */ 95 MPP43_GPIO, /* Piggy3 LED[6] */ 96 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 97 MPP45_GPIO, /* Piggy3 LED[8] */ 98 MPP46_GPIO, /* Reserved */ 99 MPP47_GPIO, /* Reserved */ 100 MPP48_GPIO, /* Reserved */ 101 MPP49_GPIO, /* SW_INTOUTn */ 102 0 103 }; 104 105 #if defined(CONFIG_KM_MGCOGE3UN) 106 /* 107 * Wait for startup OK from mgcoge3ne 108 */ 109 static int startup_allowed(void) 110 { 111 unsigned char buf; 112 113 /* 114 * Read CIRQ16 bit (bit 0) 115 */ 116 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 117 printf("%s: Error reading Boco\n", __func__); 118 else 119 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 120 return 1; 121 return 0; 122 } 123 #endif 124 125 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 126 /* 127 * All boards with PIGGY4 connected via a simple switch have ethernet always 128 * present. 129 */ 130 int ethernet_present(void) 131 { 132 return 1; 133 } 134 #else 135 int ethernet_present(void) 136 { 137 uchar buf; 138 int ret = 0; 139 140 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 141 printf("%s: Error reading Boco\n", __func__); 142 return -1; 143 } 144 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 145 ret = 1; 146 147 return ret; 148 } 149 #endif 150 151 static int initialize_unit_leds(void) 152 { 153 /* 154 * Init the unit LEDs per default they all are 155 * ok apart from bootstat 156 */ 157 uchar buf; 158 159 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 160 printf("%s: Error reading Boco\n", __func__); 161 return -1; 162 } 163 buf |= MASK_WRL_UNITRUN; 164 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 165 printf("%s: Error writing Boco\n", __func__); 166 return -1; 167 } 168 return 0; 169 } 170 171 static void set_bootcount_addr(void) 172 { 173 uchar buf[32]; 174 unsigned int bootcountaddr; 175 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 176 sprintf((char *)buf, "0x%x", bootcountaddr); 177 setenv("bootcountaddr", (char *)buf); 178 } 179 180 int misc_init_r(void) 181 { 182 #if defined(CONFIG_KM_MGCOGE3UN) 183 char *wait_for_ne; 184 wait_for_ne = getenv("waitforne"); 185 if (wait_for_ne != NULL) { 186 if (strcmp(wait_for_ne, "true") == 0) { 187 int cnt = 0; 188 int abort = 0; 189 puts("NE go: "); 190 while (startup_allowed() == 0) { 191 if (tstc()) { 192 (void) getc(); /* consume input */ 193 abort = 1; 194 break; 195 } 196 udelay(200000); 197 cnt++; 198 if (cnt == 5) 199 puts("wait\b\b\b\b"); 200 if (cnt == 10) { 201 cnt = 0; 202 puts(" \b\b\b\b"); 203 } 204 } 205 if (abort == 1) 206 printf("\nAbort waiting for ne\n"); 207 else 208 puts("OK\n"); 209 } 210 } 211 #endif 212 213 initialize_unit_leds(); 214 set_km_env(); 215 set_bootcount_addr(); 216 return 0; 217 } 218 219 int board_early_init_f(void) 220 { 221 #if defined(CONFIG_SYS_I2C_SOFT) 222 u32 tmp; 223 224 /* set the 2 bitbang i2c pins as output gpios */ 225 tmp = readl(MVEBU_GPIO0_BASE + 4); 226 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); 227 #endif 228 /* adjust SDRAM size for bank 0 */ 229 mvebu_sdram_size_adjust(0); 230 kirkwood_mpp_conf(kwmpp_config, NULL); 231 return 0; 232 } 233 234 int board_init(void) 235 { 236 /* address of boot parameters */ 237 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 238 239 /* 240 * The KM_FLASH_GPIO_PIN switches between using a 241 * NAND or a SPI FLASH. Set this pin on start 242 * to NAND mode. 243 */ 244 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 245 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 246 247 #if defined(CONFIG_SYS_I2C_SOFT) 248 /* 249 * Reinit the GPIO for I2C Bitbang driver so that the now 250 * available gpio framework is consistent. The calls to 251 * direction output in are not necessary, they are already done in 252 * board_early_init_f 253 */ 254 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 255 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 256 #endif 257 258 #if defined(CONFIG_SYS_EEPROM_WREN) 259 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 260 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 261 #endif 262 263 #if defined(CONFIG_KM_FPGA_CONFIG) 264 trigger_fpga_config(); 265 #endif 266 267 return 0; 268 } 269 270 int board_late_init(void) 271 { 272 #if defined(CONFIG_KMCOGE5UN) 273 /* I/O pin to erase flash RGPP09 = MPP43 */ 274 #define KM_FLASH_ERASE_ENABLE 43 275 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 276 277 /* if pin 1 do full erase */ 278 if (dip_switch != 0) { 279 /* start bootloader */ 280 puts("DIP: Enabled\n"); 281 setenv("actual_bank", "0"); 282 } 283 #endif 284 285 #if defined(CONFIG_KM_FPGA_CONFIG) 286 wait_for_fpga_config(); 287 fpga_reset(); 288 toggle_eeprom_spi_bus(); 289 #endif 290 return 0; 291 } 292 293 int board_spi_claim_bus(struct spi_slave *slave) 294 { 295 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 296 297 return 0; 298 } 299 300 void board_spi_release_bus(struct spi_slave *slave) 301 { 302 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 303 } 304 305 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 306 307 #define PHY_LED_SEL_REG 0x18 308 #define PHY_LED0_LINK (0x5) 309 #define PHY_LED1_ACT (0x8<<4) 310 #define PHY_LED2_INT (0xe<<8) 311 #define PHY_SPEC_CTRL_REG 0x1c 312 #define PHY_RGMII_CLK_STABLE (0x1<<10) 313 #define PHY_CLSA (0x1<<1) 314 315 /* Configure and enable MV88E3018 PHY */ 316 void reset_phy(void) 317 { 318 char *name = "egiga0"; 319 unsigned short reg; 320 321 if (miiphy_set_current_dev(name)) 322 return; 323 324 /* RGMII clk transition on data stable */ 325 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 326 printf("Error reading PHY spec ctrl reg\n"); 327 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 328 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 329 printf("Error writing PHY spec ctrl reg\n"); 330 331 /* leds setup */ 332 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 333 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 334 printf("Error writing PHY LED reg\n"); 335 336 /* reset the phy */ 337 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 338 } 339 #elif defined(CONFIG_KM_PIGGY4_88E6352) 340 341 #include <mv88e6352.h> 342 343 #if defined(CONFIG_KM_NUSA) 344 struct mv88e_sw_reg extsw_conf[] = { 345 /* 346 * port 0, PIGGY4, autoneg 347 * first the fix for the 1000Mbits Autoneg, this is from 348 * a Marvell errata, the regs are undocumented 349 */ 350 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 351 { PHY(0), PHY_STATUS, AN1000FIX }, 352 { PHY(0), PHY_PAGE, 0 }, 353 /* now the real port and phy configuration */ 354 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 355 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 356 { PHY(0), PHY_1000_CTRL, NO_ADV }, 357 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 358 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 359 FULL_DUPLEX }, 360 /* port 1, unused */ 361 { PORT(1), PORT_CTRL, PORT_DIS }, 362 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 363 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 364 /* port 2, unused */ 365 { PORT(2), PORT_CTRL, PORT_DIS }, 366 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 367 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 368 /* port 3, unused */ 369 { PORT(3), PORT_CTRL, PORT_DIS }, 370 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 371 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 372 /* port 4, ICNEV, SerDes, SGMII */ 373 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 374 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 375 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 376 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 377 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 378 /* port 5, CPU_RGMII */ 379 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 380 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 381 FULL_DPX_FOR | SPEED_1000_FOR }, 382 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 383 /* port 6, unused, this port has no phy */ 384 { PORT(6), PORT_CTRL, PORT_DIS }, 385 }; 386 #else 387 struct mv88e_sw_reg extsw_conf[] = {}; 388 #endif 389 390 void reset_phy(void) 391 { 392 #if defined(CONFIG_KM_MVEXTSW_ADDR) 393 char *name = "egiga0"; 394 395 if (miiphy_set_current_dev(name)) 396 return; 397 398 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 399 ARRAY_SIZE(extsw_conf)); 400 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 401 #endif 402 } 403 404 #else 405 /* Configure and enable MV88E1118 PHY on the piggy*/ 406 void reset_phy(void) 407 { 408 char *name = "egiga0"; 409 410 if (miiphy_set_current_dev(name)) 411 return; 412 413 /* reset the phy */ 414 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 415 } 416 #endif 417 418 419 #if defined(CONFIG_HUSH_INIT_VAR) 420 int hush_init_var(void) 421 { 422 ivm_read_eeprom(); 423 return 0; 424 } 425 #endif 426 427 #if defined(CONFIG_SYS_I2C_SOFT) 428 void set_sda(int state) 429 { 430 I2C_ACTIVE; 431 I2C_SDA(state); 432 } 433 434 void set_scl(int state) 435 { 436 I2C_SCL(state); 437 } 438 439 int get_sda(void) 440 { 441 I2C_TRISTATE; 442 return I2C_READ; 443 } 444 445 int get_scl(void) 446 { 447 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 448 } 449 #endif 450 451 #if defined(CONFIG_POST) 452 453 #define KM_POST_EN_L 44 454 #define POST_WORD_OFF 8 455 456 int post_hotkeys_pressed(void) 457 { 458 #if defined(CONFIG_KM_COGE5UN) 459 return kw_gpio_get_value(KM_POST_EN_L); 460 #else 461 return !kw_gpio_get_value(KM_POST_EN_L); 462 #endif 463 } 464 465 ulong post_word_load(void) 466 { 467 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 468 return in_le32(addr); 469 470 } 471 void post_word_store(ulong value) 472 { 473 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 474 out_le32(addr, value); 475 } 476 477 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 478 { 479 *vstart = CONFIG_SYS_SDRAM_BASE; 480 481 /* we go up to relocation plus a 1 MB margin */ 482 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 483 484 return 0; 485 } 486 #endif 487 488 #if defined(CONFIG_SYS_EEPROM_WREN) 489 int eeprom_write_enable(unsigned dev_addr, int state) 490 { 491 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 492 493 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 494 } 495 #endif 496