1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <i2c.h> 33 #include <nand.h> 34 #include <netdev.h> 35 #include <miiphy.h> 36 #include <asm/io.h> 37 #include <asm/arch/kirkwood.h> 38 #include <asm/arch/mpp.h> 39 40 #include "../common/common.h" 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* 45 * BOCO FPGA definitions 46 */ 47 #define BOCO 0x10 48 #define REG_CTRL_H 0x02 49 #define MASK_WRL_UNITRUN 0x01 50 #define MASK_RBX_PGY_PRESENT 0x40 51 #define REG_IRQ_CIRQ2 0x2d 52 #define MASK_RBI_DEFECT_16 0x01 53 54 /* Multi-Purpose Pins Functionality configuration */ 55 u32 kwmpp_config[] = { 56 MPP0_NF_IO2, 57 MPP1_NF_IO3, 58 MPP2_NF_IO4, 59 MPP3_NF_IO5, 60 MPP4_NF_IO6, 61 MPP5_NF_IO7, 62 MPP6_SYSRST_OUTn, 63 MPP7_PEX_RST_OUTn, 64 #if defined(CONFIG_SOFT_I2C) 65 MPP8_GPIO, /* SDA */ 66 MPP9_GPIO, /* SCL */ 67 #endif 68 #if defined(CONFIG_HARD_I2C) 69 MPP8_TW_SDA, 70 MPP9_TW_SCK, 71 #endif 72 MPP10_UART0_TXD, 73 MPP11_UART0_RXD, 74 MPP12_GPO, /* Reserved */ 75 MPP13_UART1_TXD, 76 MPP14_UART1_RXD, 77 MPP15_GPIO, /* Not used */ 78 MPP16_GPIO, /* Not used */ 79 MPP17_GPIO, /* Reserved */ 80 MPP18_NF_IO0, 81 MPP19_NF_IO1, 82 MPP20_GPIO, 83 MPP21_GPIO, 84 MPP22_GPIO, 85 MPP23_GPIO, 86 MPP24_GPIO, 87 MPP25_GPIO, 88 MPP26_GPIO, 89 MPP27_GPIO, 90 MPP28_GPIO, 91 MPP29_GPIO, 92 MPP30_GPIO, 93 MPP31_GPIO, 94 MPP32_GPIO, 95 MPP33_GPIO, 96 MPP34_GPIO, /* CDL1 (input) */ 97 MPP35_GPIO, /* CDL2 (input) */ 98 MPP36_GPIO, /* MAIN_IRQ (input) */ 99 MPP37_GPIO, /* BOARD_LED */ 100 MPP38_GPIO, /* Piggy3 LED[1] */ 101 MPP39_GPIO, /* Piggy3 LED[2] */ 102 MPP40_GPIO, /* Piggy3 LED[3] */ 103 MPP41_GPIO, /* Piggy3 LED[4] */ 104 MPP42_GPIO, /* Piggy3 LED[5] */ 105 MPP43_GPIO, /* Piggy3 LED[6] */ 106 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 107 MPP45_GPIO, /* Piggy3 LED[8] */ 108 MPP46_GPIO, /* Reserved */ 109 MPP47_GPIO, /* Reserved */ 110 MPP48_GPIO, /* Reserved */ 111 MPP49_GPIO, /* SW_INTOUTn */ 112 0 113 }; 114 115 #if defined(CONFIG_MGCOGE3UN) 116 /* 117 * Wait for startup OK from mgcoge3ne 118 */ 119 int startup_allowed(void) 120 { 121 unsigned char buf; 122 123 /* 124 * Read CIRQ16 bit (bit 0) 125 */ 126 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 127 printf("%s: Error reading Boco\n", __func__); 128 else 129 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 130 return 1; 131 return 0; 132 } 133 134 /* 135 * mgcoge3un has always ethernet present. Its connected to the 6061 switch 136 * and provides ICNev and piggy4 connections. 137 */ 138 int ethernet_present(void) 139 { 140 return 1; 141 } 142 #else 143 int ethernet_present(void) 144 { 145 uchar buf; 146 int ret = 0; 147 148 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 149 printf("%s: Error reading Boco\n", __func__); 150 return -1; 151 } 152 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 153 ret = 1; 154 155 return ret; 156 } 157 #endif 158 159 int initialize_unit_leds(void) 160 { 161 /* 162 * Init the unit LEDs per default they all are 163 * ok apart from bootstat 164 */ 165 uchar buf; 166 167 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 168 printf("%s: Error reading Boco\n", __func__); 169 return -1; 170 } 171 buf |= MASK_WRL_UNITRUN; 172 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 173 printf("%s: Error writing Boco\n", __func__); 174 return -1; 175 } 176 return 0; 177 } 178 179 #if defined(CONFIG_BOOTCOUNT_LIMIT) 180 void set_bootcount_addr(void) 181 { 182 uchar buf[32]; 183 unsigned int bootcountaddr; 184 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 185 sprintf((char *)buf, "0x%x", bootcountaddr); 186 setenv("bootcountaddr", (char *)buf); 187 } 188 #endif 189 190 int misc_init_r(void) 191 { 192 char *str; 193 int mach_type; 194 195 str = getenv("mach_type"); 196 if (str != NULL) { 197 mach_type = simple_strtoul(str, NULL, 10); 198 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); 199 gd->bd->bi_arch_number = mach_type; 200 } 201 #if defined(CONFIG_MGCOGE3UN) 202 char *wait_for_ne; 203 wait_for_ne = getenv("waitforne"); 204 if (wait_for_ne != NULL) { 205 if (strcmp(wait_for_ne, "true") == 0) { 206 int cnt = 0; 207 puts("NE go: "); 208 while (startup_allowed() == 0) { 209 udelay(200000); 210 cnt++; 211 if (cnt == 5) 212 puts("wait\b\b\b\b"); 213 if (cnt == 10) { 214 cnt = 0; 215 puts(" \b\b\b\b"); 216 } 217 } 218 puts("OK\n"); 219 } 220 } 221 #endif 222 223 initialize_unit_leds(); 224 set_km_env(); 225 #if defined(CONFIG_BOOTCOUNT_LIMIT) 226 set_bootcount_addr(); 227 #endif 228 return 0; 229 } 230 231 int board_early_init_f(void) 232 { 233 u32 tmp; 234 235 kirkwood_mpp_conf(kwmpp_config); 236 237 /* 238 * The FLASH_GPIO_PIN switches between using a 239 * NAND or a SPI FLASH. Set this pin on start 240 * to NAND mode. 241 */ 242 tmp = readl(KW_GPIO0_BASE); 243 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 244 tmp = readl(KW_GPIO0_BASE + 4); 245 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); 246 247 #if defined(CONFIG_SOFT_I2C) 248 /* init the GPIO for I2C Bitbang driver */ 249 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 250 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 251 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); 252 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); 253 #endif 254 #if defined(CONFIG_SYS_EEPROM_WREN) 255 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 256 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 257 #endif 258 259 return 0; 260 } 261 262 int board_init(void) 263 { 264 /* 265 * arch number of board 266 */ 267 gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; 268 269 /* address of boot parameters */ 270 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 271 272 return 0; 273 } 274 275 #if defined(CONFIG_CMD_SF) 276 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 277 { 278 u32 tmp; 279 if (argc < 2) 280 return cmd_usage(cmdtp); 281 282 if ((strcmp(argv[1], "off") == 0)) { 283 printf("SPI FLASH disabled, NAND enabled\n"); 284 /* Multi-Purpose Pins Functionality configuration */ 285 kwmpp_config[0] = MPP0_NF_IO2; 286 kwmpp_config[1] = MPP1_NF_IO3; 287 kwmpp_config[2] = MPP2_NF_IO4; 288 kwmpp_config[3] = MPP3_NF_IO5; 289 290 kirkwood_mpp_conf(kwmpp_config); 291 tmp = readl(KW_GPIO0_BASE); 292 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 293 } else if ((strcmp(argv[1], "on") == 0)) { 294 printf("SPI FLASH enabled, NAND disabled\n"); 295 /* Multi-Purpose Pins Functionality configuration */ 296 kwmpp_config[0] = MPP0_SPI_SCn; 297 kwmpp_config[1] = MPP1_SPI_MOSI; 298 kwmpp_config[2] = MPP2_SPI_SCK; 299 kwmpp_config[3] = MPP3_SPI_MISO; 300 301 kirkwood_mpp_conf(kwmpp_config); 302 tmp = readl(KW_GPIO0_BASE); 303 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); 304 } else { 305 return cmd_usage(cmdtp); 306 } 307 308 return 0; 309 } 310 311 U_BOOT_CMD( 312 spitoggle, 2, 0, do_spi_toggle, 313 "En-/disable SPI FLASH access", 314 "<on|off> - Enable (on) or disable (off) SPI FLASH access\n" 315 ); 316 #endif 317 318 int dram_init(void) 319 { 320 /* dram_init must store complete ramsize in gd->ram_size */ 321 /* Fix this */ 322 gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0), 323 kw_sdram_bs(0)); 324 return 0; 325 } 326 327 void dram_init_banksize(void) 328 { 329 int i; 330 331 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 332 gd->bd->bi_dram[i].start = kw_sdram_bar(i); 333 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), 334 kw_sdram_bs(i)); 335 } 336 } 337 338 #if defined(CONFIG_MGCOGE3UN) 339 340 #define PHY_LED_SEL 0x18 341 #define PHY_LED0_LINK (0x5) 342 #define PHY_LED1_ACT (0x8<<4) 343 #define PHY_LED2_INT (0xe<<8) 344 #define PHY_SPEC_CTRL 0x1c 345 #define PHY_RGMII_CLK_STABLE (0x1<<10) 346 #define PHY_CLSA (0x1<<1) 347 348 /* Configure and enable MV88E3018 PHY */ 349 void reset_phy(void) 350 { 351 char *name = "egiga0"; 352 unsigned short reg; 353 354 if (miiphy_set_current_dev(name)) 355 return; 356 357 /* RGMII clk transition on data stable */ 358 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) 359 printf("Error reading PHY spec ctrl reg\n"); 360 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, 361 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) 362 printf("Error writing PHY spec ctrl reg\n"); 363 364 /* leds setup */ 365 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, 366 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) 367 printf("Error writing PHY LED reg\n"); 368 369 /* reset the phy */ 370 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 371 } 372 #else 373 /* Configure and enable MV88E1118 PHY on the piggy*/ 374 void reset_phy(void) 375 { 376 char *name = "egiga0"; 377 378 if (miiphy_set_current_dev(name)) 379 return; 380 381 /* reset the phy */ 382 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 383 } 384 #endif 385 386 387 #if defined(CONFIG_HUSH_INIT_VAR) 388 int hush_init_var(void) 389 { 390 ivm_read_eeprom(); 391 return 0; 392 } 393 #endif 394 395 #if defined(CONFIG_BOOTCOUNT_LIMIT) 396 void bootcount_store(ulong a) 397 { 398 volatile ulong *save_addr; 399 volatile ulong size = 0; 400 int i; 401 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 402 size += gd->bd->bi_dram[i].size; 403 } 404 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 405 writel(a, save_addr); 406 writel(BOOTCOUNT_MAGIC, &save_addr[1]); 407 } 408 409 ulong bootcount_load(void) 410 { 411 volatile ulong *save_addr; 412 volatile ulong size = 0; 413 int i; 414 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 415 size += gd->bd->bi_dram[i].size; 416 } 417 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 418 if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC) 419 return 0; 420 else 421 return readl(save_addr); 422 } 423 #endif 424 425 #if defined(CONFIG_SOFT_I2C) 426 void set_sda(int state) 427 { 428 I2C_ACTIVE; 429 I2C_SDA(state); 430 } 431 432 void set_scl(int state) 433 { 434 I2C_SCL(state); 435 } 436 437 int get_sda(void) 438 { 439 I2C_TRISTATE; 440 return I2C_READ; 441 } 442 443 int get_scl(void) 444 { 445 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 446 } 447 #endif 448 449 #if defined(CONFIG_SYS_EEPROM_WREN) 450 int eeprom_write_enable(unsigned dev_addr, int state) 451 { 452 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 453 454 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 455 } 456 #endif 457