1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <i2c.h> 33 #include <nand.h> 34 #include <netdev.h> 35 #include <miiphy.h> 36 #include <spi.h> 37 #include <asm/io.h> 38 #include <asm/arch/cpu.h> 39 #include <asm/arch/kirkwood.h> 40 #include <asm/arch/mpp.h> 41 42 #include "../common/common.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 /* 47 * BOCO FPGA definitions 48 */ 49 #define BOCO 0x10 50 #define REG_CTRL_H 0x02 51 #define MASK_WRL_UNITRUN 0x01 52 #define MASK_RBX_PGY_PRESENT 0x40 53 #define REG_IRQ_CIRQ2 0x2d 54 #define MASK_RBI_DEFECT_16 0x01 55 56 /* Multi-Purpose Pins Functionality configuration */ 57 u32 kwmpp_config[] = { 58 MPP0_NF_IO2, 59 MPP1_NF_IO3, 60 MPP2_NF_IO4, 61 MPP3_NF_IO5, 62 MPP4_NF_IO6, 63 MPP5_NF_IO7, 64 MPP6_SYSRST_OUTn, 65 MPP7_PEX_RST_OUTn, 66 #if defined(CONFIG_SOFT_I2C) 67 MPP8_GPIO, /* SDA */ 68 MPP9_GPIO, /* SCL */ 69 #endif 70 #if defined(CONFIG_HARD_I2C) 71 MPP8_TW_SDA, 72 MPP9_TW_SCK, 73 #endif 74 MPP10_UART0_TXD, 75 MPP11_UART0_RXD, 76 MPP12_GPO, /* Reserved */ 77 MPP13_UART1_TXD, 78 MPP14_UART1_RXD, 79 MPP15_GPIO, /* Not used */ 80 MPP16_GPIO, /* Not used */ 81 MPP17_GPIO, /* Reserved */ 82 MPP18_NF_IO0, 83 MPP19_NF_IO1, 84 MPP20_GPIO, 85 MPP21_GPIO, 86 MPP22_GPIO, 87 MPP23_GPIO, 88 MPP24_GPIO, 89 MPP25_GPIO, 90 MPP26_GPIO, 91 MPP27_GPIO, 92 MPP28_GPIO, 93 MPP29_GPIO, 94 MPP30_GPIO, 95 MPP31_GPIO, 96 MPP32_GPIO, 97 MPP33_GPIO, 98 MPP34_GPIO, /* CDL1 (input) */ 99 MPP35_GPIO, /* CDL2 (input) */ 100 MPP36_GPIO, /* MAIN_IRQ (input) */ 101 MPP37_GPIO, /* BOARD_LED */ 102 MPP38_GPIO, /* Piggy3 LED[1] */ 103 MPP39_GPIO, /* Piggy3 LED[2] */ 104 MPP40_GPIO, /* Piggy3 LED[3] */ 105 MPP41_GPIO, /* Piggy3 LED[4] */ 106 MPP42_GPIO, /* Piggy3 LED[5] */ 107 MPP43_GPIO, /* Piggy3 LED[6] */ 108 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 109 MPP45_GPIO, /* Piggy3 LED[8] */ 110 MPP46_GPIO, /* Reserved */ 111 MPP47_GPIO, /* Reserved */ 112 MPP48_GPIO, /* Reserved */ 113 MPP49_GPIO, /* SW_INTOUTn */ 114 0 115 }; 116 117 #if defined(CONFIG_KM_MGCOGE3UN) 118 /* 119 * Wait for startup OK from mgcoge3ne 120 */ 121 int startup_allowed(void) 122 { 123 unsigned char buf; 124 125 /* 126 * Read CIRQ16 bit (bit 0) 127 */ 128 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 129 printf("%s: Error reading Boco\n", __func__); 130 else 131 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 132 return 1; 133 return 0; 134 } 135 #endif 136 137 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 138 /* 139 * All boards with PIGGY4 connected via a simple switch have ethernet always 140 * present. 141 */ 142 int ethernet_present(void) 143 { 144 return 1; 145 } 146 #else 147 int ethernet_present(void) 148 { 149 uchar buf; 150 int ret = 0; 151 152 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 153 printf("%s: Error reading Boco\n", __func__); 154 return -1; 155 } 156 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 157 ret = 1; 158 159 return ret; 160 } 161 #endif 162 163 int initialize_unit_leds(void) 164 { 165 /* 166 * Init the unit LEDs per default they all are 167 * ok apart from bootstat 168 */ 169 uchar buf; 170 171 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 172 printf("%s: Error reading Boco\n", __func__); 173 return -1; 174 } 175 buf |= MASK_WRL_UNITRUN; 176 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 177 printf("%s: Error writing Boco\n", __func__); 178 return -1; 179 } 180 return 0; 181 } 182 183 #if defined(CONFIG_BOOTCOUNT_LIMIT) 184 void set_bootcount_addr(void) 185 { 186 uchar buf[32]; 187 unsigned int bootcountaddr; 188 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 189 sprintf((char *)buf, "0x%x", bootcountaddr); 190 setenv("bootcountaddr", (char *)buf); 191 } 192 #endif 193 194 int misc_init_r(void) 195 { 196 char *str; 197 int mach_type; 198 199 str = getenv("mach_type"); 200 if (str != NULL) { 201 mach_type = simple_strtoul(str, NULL, 10); 202 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); 203 gd->bd->bi_arch_number = mach_type; 204 } 205 #if defined(CONFIG_KM_MGCOGE3UN) 206 char *wait_for_ne; 207 wait_for_ne = getenv("waitforne"); 208 if (wait_for_ne != NULL) { 209 if (strcmp(wait_for_ne, "true") == 0) { 210 int cnt = 0; 211 int abort = 0; 212 puts("NE go: "); 213 while (startup_allowed() == 0) { 214 if (tstc()) { 215 (void) getc(); /* consume input */ 216 abort = 1; 217 break; 218 } 219 udelay(200000); 220 cnt++; 221 if (cnt == 5) 222 puts("wait\b\b\b\b"); 223 if (cnt == 10) { 224 cnt = 0; 225 puts(" \b\b\b\b"); 226 } 227 } 228 if (abort == 1) 229 printf("\nAbort waiting for ne\n"); 230 else 231 puts("OK\n"); 232 } 233 } 234 #endif 235 236 initialize_unit_leds(); 237 set_km_env(); 238 #if defined(CONFIG_BOOTCOUNT_LIMIT) 239 set_bootcount_addr(); 240 #endif 241 return 0; 242 } 243 244 int board_early_init_f(void) 245 { 246 #if defined(CONFIG_SOFT_I2C) 247 u32 tmp; 248 249 /* set the 2 bitbang i2c pins as output gpios */ 250 tmp = readl(KW_GPIO0_BASE + 4); 251 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); 252 #endif 253 /* adjust SDRAM size for bank 0 */ 254 kw_sdram_size_adjust(0); 255 kirkwood_mpp_conf(kwmpp_config, NULL); 256 return 0; 257 } 258 259 int board_init(void) 260 { 261 /* 262 * arch number of board 263 */ 264 gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; 265 266 /* address of boot parameters */ 267 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 268 269 /* 270 * The KM_FLASH_GPIO_PIN switches between using a 271 * NAND or a SPI FLASH. Set this pin on start 272 * to NAND mode. 273 */ 274 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 275 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 276 277 #if defined(CONFIG_SOFT_I2C) 278 /* 279 * Reinit the GPIO for I2C Bitbang driver so that the now 280 * available gpio framework is consistent. The calls to 281 * direction output in are not necessary, they are already done in 282 * board_early_init_f 283 */ 284 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 285 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 286 #endif 287 288 #if defined(CONFIG_SYS_EEPROM_WREN) 289 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 290 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 291 #endif 292 293 #if defined(CONFIG_KM_FPGA_CONFIG) 294 trigger_fpga_config(); 295 #endif 296 297 return 0; 298 } 299 300 int board_late_init(void) 301 { 302 #if defined(CONFIG_KMCOGE5UN) 303 /* I/O pin to erase flash RGPP09 = MPP43 */ 304 #define KM_FLASH_ERASE_ENABLE 43 305 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 306 307 /* if pin 1 do full erase */ 308 if (dip_switch != 0) { 309 /* start bootloader */ 310 puts("DIP: Enabled\n"); 311 setenv("actual_bank", "0"); 312 } 313 #endif 314 315 #if defined(CONFIG_KM_FPGA_CONFIG) 316 wait_for_fpga_config(); 317 fpga_reset(); 318 toggle_eeprom_spi_bus(); 319 #endif 320 return 0; 321 } 322 323 int board_spi_claim_bus(struct spi_slave *slave) 324 { 325 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 326 327 return 0; 328 } 329 330 void board_spi_release_bus(struct spi_slave *slave) 331 { 332 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 333 } 334 335 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 336 337 #define PHY_LED_SEL_REG 0x18 338 #define PHY_LED0_LINK (0x5) 339 #define PHY_LED1_ACT (0x8<<4) 340 #define PHY_LED2_INT (0xe<<8) 341 #define PHY_SPEC_CTRL_REG 0x1c 342 #define PHY_RGMII_CLK_STABLE (0x1<<10) 343 #define PHY_CLSA (0x1<<1) 344 345 /* Configure and enable MV88E3018 PHY */ 346 void reset_phy(void) 347 { 348 char *name = "egiga0"; 349 unsigned short reg; 350 351 if (miiphy_set_current_dev(name)) 352 return; 353 354 /* RGMII clk transition on data stable */ 355 if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 356 printf("Error reading PHY spec ctrl reg\n"); 357 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 358 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 359 printf("Error writing PHY spec ctrl reg\n"); 360 361 /* leds setup */ 362 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 363 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 364 printf("Error writing PHY LED reg\n"); 365 366 /* reset the phy */ 367 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 368 } 369 #elif defined(CONFIG_KM_PIGGY4_88E6352) 370 371 #include <mv88e6352.h> 372 373 #if defined(CONFIG_KM_NUSA) 374 struct mv88e_sw_reg extsw_conf[] = { 375 /* 376 * port 0, PIGGY4, autoneg 377 * first the fix for the 1000Mbits Autoneg, this is from 378 * a Marvell errata, the regs are undocumented 379 */ 380 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 381 { PHY(0), PHY_STATUS, AN1000FIX }, 382 { PHY(0), PHY_PAGE, 0 }, 383 /* now the real port and phy configuration */ 384 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 385 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 386 { PHY(0), PHY_1000_CTRL, NO_ADV }, 387 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 388 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 389 FULL_DUPLEX }, 390 /* port 1, unused */ 391 { PORT(1), PORT_CTRL, PORT_DIS }, 392 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 393 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 394 /* port 2, unused */ 395 { PORT(2), PORT_CTRL, PORT_DIS }, 396 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 397 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 398 /* port 3, unused */ 399 { PORT(3), PORT_CTRL, PORT_DIS }, 400 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 401 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 402 /* port 4, ICNEV, SerDes, SGMII */ 403 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 404 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 405 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 406 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 407 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 408 /* port 5, CPU_RGMII */ 409 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 410 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 411 FULL_DPX_FOR | SPEED_1000_FOR }, 412 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 413 /* port 6, unused, this port has no phy */ 414 { PORT(6), PORT_CTRL, PORT_DIS }, 415 }; 416 #else 417 struct mv88e_sw_reg extsw_conf[] = {}; 418 #endif 419 420 void reset_phy(void) 421 { 422 #if defined(CONFIG_KM_MVEXTSW_ADDR) 423 char *name = "egiga0"; 424 425 if (miiphy_set_current_dev(name)) 426 return; 427 428 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 429 ARRAY_SIZE(extsw_conf)); 430 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 431 #endif 432 } 433 434 #else 435 /* Configure and enable MV88E1118 PHY on the piggy*/ 436 void reset_phy(void) 437 { 438 char *name = "egiga0"; 439 440 if (miiphy_set_current_dev(name)) 441 return; 442 443 /* reset the phy */ 444 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 445 } 446 #endif 447 448 449 #if defined(CONFIG_HUSH_INIT_VAR) 450 int hush_init_var(void) 451 { 452 ivm_read_eeprom(); 453 return 0; 454 } 455 #endif 456 457 #if defined(CONFIG_SOFT_I2C) 458 void set_sda(int state) 459 { 460 I2C_ACTIVE; 461 I2C_SDA(state); 462 } 463 464 void set_scl(int state) 465 { 466 I2C_SCL(state); 467 } 468 469 int get_sda(void) 470 { 471 I2C_TRISTATE; 472 return I2C_READ; 473 } 474 475 int get_scl(void) 476 { 477 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 478 } 479 #endif 480 481 #if defined(CONFIG_POST) 482 483 #define KM_POST_EN_L 44 484 #define POST_WORD_OFF 8 485 486 int post_hotkeys_pressed(void) 487 { 488 #if defined(CONFIG_KM_COGE5UN) 489 return kw_gpio_get_value(KM_POST_EN_L); 490 #else 491 return !kw_gpio_get_value(KM_POST_EN_L); 492 #endif 493 } 494 495 ulong post_word_load(void) 496 { 497 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 498 return in_le32(addr); 499 500 } 501 void post_word_store(ulong value) 502 { 503 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 504 out_le32(addr, value); 505 } 506 507 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 508 { 509 *vstart = CONFIG_SYS_SDRAM_BASE; 510 511 /* we go up to relocation plus a 1 MB margin */ 512 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 513 514 return 0; 515 } 516 #endif 517 518 #if defined(CONFIG_SYS_EEPROM_WREN) 519 int eeprom_write_enable(unsigned dev_addr, int state) 520 { 521 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 522 523 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 524 } 525 #endif 526