1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <nand.h> 18 #include <netdev.h> 19 #include <miiphy.h> 20 #include <spi.h> 21 #include <asm/io.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/soc.h> 24 #include <asm/arch/mpp.h> 25 26 #include "../common/common.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * BOCO FPGA definitions 32 */ 33 #define BOCO 0x10 34 #define REG_CTRL_H 0x02 35 #define MASK_WRL_UNITRUN 0x01 36 #define MASK_RBX_PGY_PRESENT 0x40 37 #define REG_IRQ_CIRQ2 0x2d 38 #define MASK_RBI_DEFECT_16 0x01 39 40 /* 41 * PHY registers definitions 42 */ 43 #define PHY_MARVELL_OUI 0x5043 44 #define PHY_MARVELL_88E1118_MODEL 0x0022 45 #define PHY_MARVELL_88E1118R_MODEL 0x0024 46 47 #define PHY_MARVELL_PAGE_REG 0x0016 48 #define PHY_MARVELL_DEFAULT_PAGE 0x0000 49 50 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003 51 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010 52 53 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000 54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0) 55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4) 56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8) 57 58 /* I/O pin to erase flash RGPP09 = MPP43 */ 59 #define KM_FLASH_ERASE_ENABLE 43 60 61 /* Multi-Purpose Pins Functionality configuration */ 62 static const u32 kwmpp_config[] = { 63 MPP0_NF_IO2, 64 MPP1_NF_IO3, 65 MPP2_NF_IO4, 66 MPP3_NF_IO5, 67 MPP4_NF_IO6, 68 MPP5_NF_IO7, 69 MPP6_SYSRST_OUTn, 70 #if defined(KM_PCIE_RESET_MPP7) 71 MPP7_GPO, 72 #else 73 MPP7_PEX_RST_OUTn, 74 #endif 75 #if defined(CONFIG_SYS_I2C_SOFT) 76 MPP8_GPIO, /* SDA */ 77 MPP9_GPIO, /* SCL */ 78 #endif 79 #if defined(CONFIG_HARD_I2C) 80 MPP8_TW_SDA, 81 MPP9_TW_SCK, 82 #endif 83 MPP10_UART0_TXD, 84 MPP11_UART0_RXD, 85 MPP12_GPO, /* Reserved */ 86 MPP13_UART1_TXD, 87 MPP14_UART1_RXD, 88 MPP15_GPIO, /* Not used */ 89 MPP16_GPIO, /* Not used */ 90 MPP17_GPIO, /* Reserved */ 91 MPP18_NF_IO0, 92 MPP19_NF_IO1, 93 MPP20_GPIO, 94 MPP21_GPIO, 95 MPP22_GPIO, 96 MPP23_GPIO, 97 MPP24_GPIO, 98 MPP25_GPIO, 99 MPP26_GPIO, 100 MPP27_GPIO, 101 MPP28_GPIO, 102 MPP29_GPIO, 103 MPP30_GPIO, 104 MPP31_GPIO, 105 MPP32_GPIO, 106 MPP33_GPIO, 107 MPP34_GPIO, /* CDL1 (input) */ 108 MPP35_GPIO, /* CDL2 (input) */ 109 MPP36_GPIO, /* MAIN_IRQ (input) */ 110 MPP37_GPIO, /* BOARD_LED */ 111 MPP38_GPIO, /* Piggy3 LED[1] */ 112 MPP39_GPIO, /* Piggy3 LED[2] */ 113 MPP40_GPIO, /* Piggy3 LED[3] */ 114 MPP41_GPIO, /* Piggy3 LED[4] */ 115 MPP42_GPIO, /* Piggy3 LED[5] */ 116 MPP43_GPIO, /* Piggy3 LED[6] */ 117 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 118 MPP45_GPIO, /* Piggy3 LED[8] */ 119 MPP46_GPIO, /* Reserved */ 120 MPP47_GPIO, /* Reserved */ 121 MPP48_GPIO, /* Reserved */ 122 MPP49_GPIO, /* SW_INTOUTn */ 123 0 124 }; 125 126 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; 127 128 #if defined(CONFIG_KM_MGCOGE3UN) 129 /* 130 * Wait for startup OK from mgcoge3ne 131 */ 132 static int startup_allowed(void) 133 { 134 unsigned char buf; 135 136 /* 137 * Read CIRQ16 bit (bit 0) 138 */ 139 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 140 printf("%s: Error reading Boco\n", __func__); 141 else 142 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 143 return 1; 144 return 0; 145 } 146 #endif 147 148 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 149 /* 150 * All boards with PIGGY4 connected via a simple switch have ethernet always 151 * present. 152 */ 153 int ethernet_present(void) 154 { 155 return 1; 156 } 157 #else 158 int ethernet_present(void) 159 { 160 uchar buf; 161 int ret = 0; 162 163 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 164 printf("%s: Error reading Boco\n", __func__); 165 return -1; 166 } 167 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 168 ret = 1; 169 170 return ret; 171 } 172 #endif 173 174 static int initialize_unit_leds(void) 175 { 176 /* 177 * Init the unit LEDs per default they all are 178 * ok apart from bootstat 179 */ 180 uchar buf; 181 182 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 183 printf("%s: Error reading Boco\n", __func__); 184 return -1; 185 } 186 buf |= MASK_WRL_UNITRUN; 187 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 188 printf("%s: Error writing Boco\n", __func__); 189 return -1; 190 } 191 return 0; 192 } 193 194 static void set_bootcount_addr(void) 195 { 196 uchar buf[32]; 197 unsigned int bootcountaddr; 198 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 199 sprintf((char *)buf, "0x%x", bootcountaddr); 200 setenv("bootcountaddr", (char *)buf); 201 } 202 203 int misc_init_r(void) 204 { 205 #if defined(CONFIG_KM_MGCOGE3UN) 206 char *wait_for_ne; 207 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 208 wait_for_ne = getenv("waitforne"); 209 210 if ((wait_for_ne != NULL) && (dip_switch == 0)) { 211 if (strcmp(wait_for_ne, "true") == 0) { 212 int cnt = 0; 213 int abort = 0; 214 puts("NE go: "); 215 while (startup_allowed() == 0) { 216 if (tstc()) { 217 (void) getc(); /* consume input */ 218 abort = 1; 219 break; 220 } 221 udelay(200000); 222 cnt++; 223 if (cnt == 5) 224 puts("wait\b\b\b\b"); 225 if (cnt == 10) { 226 cnt = 0; 227 puts(" \b\b\b\b"); 228 } 229 } 230 if (abort == 1) 231 printf("\nAbort waiting for ne\n"); 232 else 233 puts("OK\n"); 234 } 235 } 236 #endif 237 238 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 239 240 initialize_unit_leds(); 241 set_km_env(); 242 set_bootcount_addr(); 243 return 0; 244 } 245 246 int board_early_init_f(void) 247 { 248 #if defined(CONFIG_SYS_I2C_SOFT) 249 u32 tmp; 250 251 /* set the 2 bitbang i2c pins as output gpios */ 252 tmp = readl(MVEBU_GPIO0_BASE + 4); 253 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); 254 #endif 255 /* adjust SDRAM size for bank 0 */ 256 mvebu_sdram_size_adjust(0); 257 kirkwood_mpp_conf(kwmpp_config, NULL); 258 return 0; 259 } 260 261 int board_init(void) 262 { 263 /* address of boot parameters */ 264 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 265 266 /* 267 * The KM_FLASH_GPIO_PIN switches between using a 268 * NAND or a SPI FLASH. Set this pin on start 269 * to NAND mode. 270 */ 271 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 272 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 273 274 #if defined(CONFIG_SYS_I2C_SOFT) 275 /* 276 * Reinit the GPIO for I2C Bitbang driver so that the now 277 * available gpio framework is consistent. The calls to 278 * direction output in are not necessary, they are already done in 279 * board_early_init_f 280 */ 281 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 282 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 283 #endif 284 285 #if defined(CONFIG_SYS_EEPROM_WREN) 286 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 287 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 288 #endif 289 290 #if defined(CONFIG_KM_FPGA_CONFIG) 291 trigger_fpga_config(); 292 #endif 293 294 return 0; 295 } 296 297 int board_late_init(void) 298 { 299 #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN)) 300 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 301 302 /* if pin 1 do full erase */ 303 if (dip_switch != 0) { 304 /* start bootloader */ 305 puts("DIP: Enabled\n"); 306 setenv("actual_bank", "0"); 307 } 308 #endif 309 310 #if defined(CONFIG_KM_FPGA_CONFIG) 311 wait_for_fpga_config(); 312 fpga_reset(); 313 toggle_eeprom_spi_bus(); 314 #endif 315 return 0; 316 } 317 318 int board_spi_claim_bus(struct spi_slave *slave) 319 { 320 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 321 322 return 0; 323 } 324 325 void board_spi_release_bus(struct spi_slave *slave) 326 { 327 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 328 } 329 330 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 331 332 #define PHY_LED_SEL_REG 0x18 333 #define PHY_LED0_LINK (0x5) 334 #define PHY_LED1_ACT (0x8<<4) 335 #define PHY_LED2_INT (0xe<<8) 336 #define PHY_SPEC_CTRL_REG 0x1c 337 #define PHY_RGMII_CLK_STABLE (0x1<<10) 338 #define PHY_CLSA (0x1<<1) 339 340 /* Configure and enable MV88E3018 PHY */ 341 void reset_phy(void) 342 { 343 char *name = "egiga0"; 344 unsigned short reg; 345 346 if (miiphy_set_current_dev(name)) 347 return; 348 349 /* RGMII clk transition on data stable */ 350 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 351 printf("Error reading PHY spec ctrl reg\n"); 352 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 353 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 354 printf("Error writing PHY spec ctrl reg\n"); 355 356 /* leds setup */ 357 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 358 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 359 printf("Error writing PHY LED reg\n"); 360 361 /* reset the phy */ 362 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 363 } 364 #elif defined(CONFIG_KM_PIGGY4_88E6352) 365 366 #include <mv88e6352.h> 367 368 #if defined(CONFIG_KM_NUSA) 369 struct mv88e_sw_reg extsw_conf[] = { 370 /* 371 * port 0, PIGGY4, autoneg 372 * first the fix for the 1000Mbits Autoneg, this is from 373 * a Marvell errata, the regs are undocumented 374 */ 375 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 376 { PHY(0), PHY_STATUS, AN1000FIX }, 377 { PHY(0), PHY_PAGE, 0 }, 378 /* now the real port and phy configuration */ 379 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 380 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 381 { PHY(0), PHY_1000_CTRL, NO_ADV }, 382 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 383 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 384 FULL_DUPLEX }, 385 /* port 1, unused */ 386 { PORT(1), PORT_CTRL, PORT_DIS }, 387 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 388 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 389 /* port 2, unused */ 390 { PORT(2), PORT_CTRL, PORT_DIS }, 391 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 392 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 393 /* port 3, unused */ 394 { PORT(3), PORT_CTRL, PORT_DIS }, 395 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 396 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 397 /* port 4, ICNEV, SerDes, SGMII */ 398 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 399 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 400 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 401 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 402 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 403 /* port 5, CPU_RGMII */ 404 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 405 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 406 FULL_DPX_FOR | SPEED_1000_FOR }, 407 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 408 /* port 6, unused, this port has no phy */ 409 { PORT(6), PORT_CTRL, PORT_DIS }, 410 }; 411 #else 412 struct mv88e_sw_reg extsw_conf[] = {}; 413 #endif 414 415 void reset_phy(void) 416 { 417 #if defined(CONFIG_KM_MVEXTSW_ADDR) 418 char *name = "egiga0"; 419 420 if (miiphy_set_current_dev(name)) 421 return; 422 423 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 424 ARRAY_SIZE(extsw_conf)); 425 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 426 #endif 427 } 428 429 #else 430 /* Configure and enable MV88E1118 PHY on the piggy*/ 431 void reset_phy(void) 432 { 433 unsigned int oui; 434 unsigned char model, rev; 435 436 char *name = "egiga0"; 437 438 if (miiphy_set_current_dev(name)) 439 return; 440 441 /* reset the phy */ 442 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 443 444 /* get PHY model */ 445 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev)) 446 return; 447 448 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */ 449 if ((oui == PHY_MARVELL_OUI) && 450 (model == PHY_MARVELL_88E1118R_MODEL)) { 451 /* set page register to 3 */ 452 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 453 PHY_MARVELL_PAGE_REG, 454 PHY_MARVELL_88E1118R_LED_CTRL_PAGE)) 455 printf("Error writing PHY page reg\n"); 456 457 /* 458 * leds setup as printed on PCB: 459 * LED2 (Link): 0x0 (On Link, Off No Link) 460 * LED1 (Activity): 0x3 (On Activity, Off No Activity) 461 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else) 462 */ 463 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 464 PHY_MARVELL_88E1118R_LED_CTRL_REG, 465 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED | 466 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB | 467 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT | 468 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK)) 469 printf("Error writing PHY LED reg\n"); 470 471 /* set page register back to 0 */ 472 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, 473 PHY_MARVELL_PAGE_REG, 474 PHY_MARVELL_DEFAULT_PAGE)) 475 printf("Error writing PHY page reg\n"); 476 } 477 } 478 #endif 479 480 481 #if defined(CONFIG_HUSH_INIT_VAR) 482 int hush_init_var(void) 483 { 484 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 485 return 0; 486 } 487 #endif 488 489 #if defined(CONFIG_SYS_I2C_SOFT) 490 void set_sda(int state) 491 { 492 I2C_ACTIVE; 493 I2C_SDA(state); 494 } 495 496 void set_scl(int state) 497 { 498 I2C_SCL(state); 499 } 500 501 int get_sda(void) 502 { 503 I2C_TRISTATE; 504 return I2C_READ; 505 } 506 507 int get_scl(void) 508 { 509 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 510 } 511 #endif 512 513 #if defined(CONFIG_POST) 514 515 #define KM_POST_EN_L 44 516 #define POST_WORD_OFF 8 517 518 int post_hotkeys_pressed(void) 519 { 520 #if defined(CONFIG_KM_COGE5UN) 521 return kw_gpio_get_value(KM_POST_EN_L); 522 #else 523 return !kw_gpio_get_value(KM_POST_EN_L); 524 #endif 525 } 526 527 ulong post_word_load(void) 528 { 529 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 530 return in_le32(addr); 531 532 } 533 void post_word_store(ulong value) 534 { 535 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 536 out_le32(addr, value); 537 } 538 539 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 540 { 541 *vstart = CONFIG_SYS_SDRAM_BASE; 542 543 /* we go up to relocation plus a 1 MB margin */ 544 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 545 546 return 0; 547 } 548 #endif 549 550 #if defined(CONFIG_SYS_EEPROM_WREN) 551 int eeprom_write_enable(unsigned dev_addr, int state) 552 { 553 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 554 555 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 556 } 557 #endif 558