1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <i2c.h> 33 #include <nand.h> 34 #include <netdev.h> 35 #include <miiphy.h> 36 #include <asm/io.h> 37 #include <asm/arch/cpu.h> 38 #include <asm/arch/kirkwood.h> 39 #include <asm/arch/mpp.h> 40 41 #include "../common/common.h" 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* 46 * BOCO FPGA definitions 47 */ 48 #define BOCO 0x10 49 #define REG_CTRL_H 0x02 50 #define MASK_WRL_UNITRUN 0x01 51 #define MASK_RBX_PGY_PRESENT 0x40 52 #define REG_IRQ_CIRQ2 0x2d 53 #define MASK_RBI_DEFECT_16 0x01 54 55 /* Multi-Purpose Pins Functionality configuration */ 56 u32 kwmpp_config[] = { 57 MPP0_NF_IO2, 58 MPP1_NF_IO3, 59 MPP2_NF_IO4, 60 MPP3_NF_IO5, 61 MPP4_NF_IO6, 62 MPP5_NF_IO7, 63 MPP6_SYSRST_OUTn, 64 MPP7_PEX_RST_OUTn, 65 #if defined(CONFIG_SOFT_I2C) 66 MPP8_GPIO, /* SDA */ 67 MPP9_GPIO, /* SCL */ 68 #endif 69 #if defined(CONFIG_HARD_I2C) 70 MPP8_TW_SDA, 71 MPP9_TW_SCK, 72 #endif 73 MPP10_UART0_TXD, 74 MPP11_UART0_RXD, 75 MPP12_GPO, /* Reserved */ 76 MPP13_UART1_TXD, 77 MPP14_UART1_RXD, 78 MPP15_GPIO, /* Not used */ 79 MPP16_GPIO, /* Not used */ 80 MPP17_GPIO, /* Reserved */ 81 MPP18_NF_IO0, 82 MPP19_NF_IO1, 83 MPP20_GPIO, 84 MPP21_GPIO, 85 MPP22_GPIO, 86 MPP23_GPIO, 87 MPP24_GPIO, 88 MPP25_GPIO, 89 MPP26_GPIO, 90 MPP27_GPIO, 91 MPP28_GPIO, 92 MPP29_GPIO, 93 MPP30_GPIO, 94 MPP31_GPIO, 95 MPP32_GPIO, 96 MPP33_GPIO, 97 MPP34_GPIO, /* CDL1 (input) */ 98 MPP35_GPIO, /* CDL2 (input) */ 99 MPP36_GPIO, /* MAIN_IRQ (input) */ 100 MPP37_GPIO, /* BOARD_LED */ 101 MPP38_GPIO, /* Piggy3 LED[1] */ 102 MPP39_GPIO, /* Piggy3 LED[2] */ 103 MPP40_GPIO, /* Piggy3 LED[3] */ 104 MPP41_GPIO, /* Piggy3 LED[4] */ 105 MPP42_GPIO, /* Piggy3 LED[5] */ 106 MPP43_GPIO, /* Piggy3 LED[6] */ 107 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 108 MPP45_GPIO, /* Piggy3 LED[8] */ 109 MPP46_GPIO, /* Reserved */ 110 MPP47_GPIO, /* Reserved */ 111 MPP48_GPIO, /* Reserved */ 112 MPP49_GPIO, /* SW_INTOUTn */ 113 0 114 }; 115 116 #if defined(CONFIG_MGCOGE3UN) 117 /* 118 * Wait for startup OK from mgcoge3ne 119 */ 120 int startup_allowed(void) 121 { 122 unsigned char buf; 123 124 /* 125 * Read CIRQ16 bit (bit 0) 126 */ 127 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 128 printf("%s: Error reading Boco\n", __func__); 129 else 130 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 131 return 1; 132 return 0; 133 } 134 #endif 135 136 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) 137 /* 138 * These two boards have always ethernet present. Its connected to the mv 139 * switch. 140 */ 141 int ethernet_present(void) 142 { 143 return 1; 144 } 145 #else 146 int ethernet_present(void) 147 { 148 uchar buf; 149 int ret = 0; 150 151 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 152 printf("%s: Error reading Boco\n", __func__); 153 return -1; 154 } 155 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 156 ret = 1; 157 158 return ret; 159 } 160 #endif 161 162 int initialize_unit_leds(void) 163 { 164 /* 165 * Init the unit LEDs per default they all are 166 * ok apart from bootstat 167 */ 168 uchar buf; 169 170 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 171 printf("%s: Error reading Boco\n", __func__); 172 return -1; 173 } 174 buf |= MASK_WRL_UNITRUN; 175 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 176 printf("%s: Error writing Boco\n", __func__); 177 return -1; 178 } 179 return 0; 180 } 181 182 #if defined(CONFIG_BOOTCOUNT_LIMIT) 183 void set_bootcount_addr(void) 184 { 185 uchar buf[32]; 186 unsigned int bootcountaddr; 187 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 188 sprintf((char *)buf, "0x%x", bootcountaddr); 189 setenv("bootcountaddr", (char *)buf); 190 } 191 #endif 192 193 int misc_init_r(void) 194 { 195 char *str; 196 int mach_type; 197 198 str = getenv("mach_type"); 199 if (str != NULL) { 200 mach_type = simple_strtoul(str, NULL, 10); 201 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); 202 gd->bd->bi_arch_number = mach_type; 203 } 204 #if defined(CONFIG_MGCOGE3UN) 205 char *wait_for_ne; 206 wait_for_ne = getenv("waitforne"); 207 if (wait_for_ne != NULL) { 208 if (strcmp(wait_for_ne, "true") == 0) { 209 int cnt = 0; 210 puts("NE go: "); 211 while (startup_allowed() == 0) { 212 udelay(200000); 213 cnt++; 214 if (cnt == 5) 215 puts("wait\b\b\b\b"); 216 if (cnt == 10) { 217 cnt = 0; 218 puts(" \b\b\b\b"); 219 } 220 } 221 puts("OK\n"); 222 } 223 } 224 #endif 225 226 initialize_unit_leds(); 227 set_km_env(); 228 #if defined(CONFIG_BOOTCOUNT_LIMIT) 229 set_bootcount_addr(); 230 #endif 231 return 0; 232 } 233 234 int board_early_init_f(void) 235 { 236 u32 tmp; 237 238 kirkwood_mpp_conf(kwmpp_config); 239 240 /* 241 * The FLASH_GPIO_PIN switches between using a 242 * NAND or a SPI FLASH. Set this pin on start 243 * to NAND mode. 244 */ 245 tmp = readl(KW_GPIO0_BASE); 246 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 247 tmp = readl(KW_GPIO0_BASE + 4); 248 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); 249 250 #if defined(CONFIG_SOFT_I2C) 251 /* init the GPIO for I2C Bitbang driver */ 252 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 253 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 254 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); 255 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); 256 #endif 257 #if defined(CONFIG_SYS_EEPROM_WREN) 258 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 259 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 260 #endif 261 262 return 0; 263 } 264 265 int board_init(void) 266 { 267 /* 268 * arch number of board 269 */ 270 gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; 271 272 /* address of boot parameters */ 273 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 274 275 return 0; 276 } 277 278 #if defined(CONFIG_CMD_SF) 279 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 280 { 281 u32 tmp; 282 if (argc < 2) 283 return cmd_usage(cmdtp); 284 285 if ((strcmp(argv[1], "off") == 0)) { 286 printf("SPI FLASH disabled, NAND enabled\n"); 287 /* Multi-Purpose Pins Functionality configuration */ 288 kwmpp_config[0] = MPP0_NF_IO2; 289 kwmpp_config[1] = MPP1_NF_IO3; 290 kwmpp_config[2] = MPP2_NF_IO4; 291 kwmpp_config[3] = MPP3_NF_IO5; 292 293 kirkwood_mpp_conf(kwmpp_config); 294 tmp = readl(KW_GPIO0_BASE); 295 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 296 } else if ((strcmp(argv[1], "on") == 0)) { 297 printf("SPI FLASH enabled, NAND disabled\n"); 298 /* Multi-Purpose Pins Functionality configuration */ 299 kwmpp_config[0] = MPP0_SPI_SCn; 300 kwmpp_config[1] = MPP1_SPI_MOSI; 301 kwmpp_config[2] = MPP2_SPI_SCK; 302 kwmpp_config[3] = MPP3_SPI_MISO; 303 304 kirkwood_mpp_conf(kwmpp_config); 305 tmp = readl(KW_GPIO0_BASE); 306 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); 307 } else { 308 return cmd_usage(cmdtp); 309 } 310 311 return 0; 312 } 313 314 U_BOOT_CMD( 315 spitoggle, 2, 0, do_spi_toggle, 316 "En-/disable SPI FLASH access", 317 "<on|off> - Enable (on) or disable (off) SPI FLASH access\n" 318 ); 319 #endif 320 321 int dram_init(void) 322 { 323 /* dram_init must store complete ramsize in gd->ram_size */ 324 /* Fix this */ 325 gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), 326 kw_sdram_bs(0)); 327 return 0; 328 } 329 330 void dram_init_banksize(void) 331 { 332 int i; 333 334 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 335 gd->bd->bi_dram[i].start = kw_sdram_bar(i); 336 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), 337 kw_sdram_bs(i)); 338 } 339 } 340 341 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) 342 343 #define PHY_LED_SEL 0x18 344 #define PHY_LED0_LINK (0x5) 345 #define PHY_LED1_ACT (0x8<<4) 346 #define PHY_LED2_INT (0xe<<8) 347 #define PHY_SPEC_CTRL 0x1c 348 #define PHY_RGMII_CLK_STABLE (0x1<<10) 349 #define PHY_CLSA (0x1<<1) 350 351 /* Configure and enable MV88E3018 PHY */ 352 void reset_phy(void) 353 { 354 char *name = "egiga0"; 355 unsigned short reg; 356 357 if (miiphy_set_current_dev(name)) 358 return; 359 360 /* RGMII clk transition on data stable */ 361 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) 362 printf("Error reading PHY spec ctrl reg\n"); 363 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, 364 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) 365 printf("Error writing PHY spec ctrl reg\n"); 366 367 /* leds setup */ 368 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, 369 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) 370 printf("Error writing PHY LED reg\n"); 371 372 /* reset the phy */ 373 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 374 } 375 #else 376 /* Configure and enable MV88E1118 PHY on the piggy*/ 377 void reset_phy(void) 378 { 379 char *name = "egiga0"; 380 381 if (miiphy_set_current_dev(name)) 382 return; 383 384 /* reset the phy */ 385 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 386 } 387 #endif 388 389 390 #if defined(CONFIG_HUSH_INIT_VAR) 391 int hush_init_var(void) 392 { 393 ivm_read_eeprom(); 394 return 0; 395 } 396 #endif 397 398 #if defined(CONFIG_BOOTCOUNT_LIMIT) 399 void bootcount_store(ulong a) 400 { 401 volatile ulong *save_addr; 402 volatile ulong size = 0; 403 int i; 404 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 405 size += gd->bd->bi_dram[i].size; 406 } 407 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 408 writel(a, save_addr); 409 writel(BOOTCOUNT_MAGIC, &save_addr[1]); 410 } 411 412 ulong bootcount_load(void) 413 { 414 volatile ulong *save_addr; 415 volatile ulong size = 0; 416 int i; 417 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 418 size += gd->bd->bi_dram[i].size; 419 } 420 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 421 if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC) 422 return 0; 423 else 424 return readl(save_addr); 425 } 426 #endif 427 428 #if defined(CONFIG_SOFT_I2C) 429 void set_sda(int state) 430 { 431 I2C_ACTIVE; 432 I2C_SDA(state); 433 } 434 435 void set_scl(int state) 436 { 437 I2C_SCL(state); 438 } 439 440 int get_sda(void) 441 { 442 I2C_TRISTATE; 443 return I2C_READ; 444 } 445 446 int get_scl(void) 447 { 448 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 449 } 450 #endif 451 452 #if defined(CONFIG_POST) 453 454 #define KM_POST_EN_L 44 455 #define POST_WORD_OFF 8 456 457 int post_hotkeys_pressed(void) 458 { 459 return !kw_gpio_get_value(KM_POST_EN_L); 460 } 461 462 ulong post_word_load(void) 463 { 464 volatile void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 465 return in_le32(addr); 466 467 } 468 void post_word_store(ulong value) 469 { 470 volatile void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 471 out_le32(addr, value); 472 } 473 474 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 475 { 476 *vstart = CONFIG_SYS_SDRAM_BASE; 477 478 /* we go up to relocation plus a 1 MB margin */ 479 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 480 481 return 0; 482 } 483 #endif 484 485 #if defined(CONFIG_SYS_EEPROM_WREN) 486 int eeprom_write_enable(unsigned dev_addr, int state) 487 { 488 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 489 490 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 491 } 492 #endif 493