xref: /openbmc/u-boot/board/keymile/km_arm/km_arm.c (revision 34a31bf5) 
1 /*
2  * (C) Copyright 2009
3  * Marvell Semiconductor <www.marvell.com>
4  * Prafulla Wadaskar <prafulla@marvell.com>
5  *
6  * (C) Copyright 2009
7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
8  *
9  * (C) Copyright 2010
10  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
11  *
12  * See file CREDITS for list of people who contributed to this
13  * project.
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License as
17  * published by the Free Software Foundation; either version 2 of
18  * the License, or (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28  * MA 02110-1301 USA
29  */
30 
31 #include <common.h>
32 #include <i2c.h>
33 #include <nand.h>
34 #include <netdev.h>
35 #include <miiphy.h>
36 #include <spi.h>
37 #include <asm/io.h>
38 #include <asm/arch/cpu.h>
39 #include <asm/arch/kirkwood.h>
40 #include <asm/arch/mpp.h>
41 
42 #include "../common/common.h"
43 
44 DECLARE_GLOBAL_DATA_PTR;
45 
46 /*
47  * BOCO FPGA definitions
48  */
49 #define BOCO		0x10
50 #define REG_CTRL_H		0x02
51 #define MASK_WRL_UNITRUN	0x01
52 #define MASK_RBX_PGY_PRESENT	0x40
53 #define REG_IRQ_CIRQ2		0x2d
54 #define MASK_RBI_DEFECT_16	0x01
55 
56 /* Multi-Purpose Pins Functionality configuration */
57 u32 kwmpp_config[] = {
58 	MPP0_NF_IO2,
59 	MPP1_NF_IO3,
60 	MPP2_NF_IO4,
61 	MPP3_NF_IO5,
62 	MPP4_NF_IO6,
63 	MPP5_NF_IO7,
64 	MPP6_SYSRST_OUTn,
65 	MPP7_PEX_RST_OUTn,
66 #if defined(CONFIG_SOFT_I2C)
67 	MPP8_GPIO,		/* SDA */
68 	MPP9_GPIO,		/* SCL */
69 #endif
70 #if defined(CONFIG_HARD_I2C)
71 	MPP8_TW_SDA,
72 	MPP9_TW_SCK,
73 #endif
74 	MPP10_UART0_TXD,
75 	MPP11_UART0_RXD,
76 	MPP12_GPO,		/* Reserved */
77 	MPP13_UART1_TXD,
78 	MPP14_UART1_RXD,
79 	MPP15_GPIO,		/* Not used */
80 	MPP16_GPIO,		/* Not used */
81 	MPP17_GPIO,		/* Reserved */
82 	MPP18_NF_IO0,
83 	MPP19_NF_IO1,
84 	MPP20_GPIO,
85 	MPP21_GPIO,
86 	MPP22_GPIO,
87 	MPP23_GPIO,
88 	MPP24_GPIO,
89 	MPP25_GPIO,
90 	MPP26_GPIO,
91 	MPP27_GPIO,
92 	MPP28_GPIO,
93 	MPP29_GPIO,
94 	MPP30_GPIO,
95 	MPP31_GPIO,
96 	MPP32_GPIO,
97 	MPP33_GPIO,
98 	MPP34_GPIO,		/* CDL1 (input) */
99 	MPP35_GPIO,		/* CDL2 (input) */
100 	MPP36_GPIO,		/* MAIN_IRQ (input) */
101 	MPP37_GPIO,		/* BOARD_LED */
102 	MPP38_GPIO,		/* Piggy3 LED[1] */
103 	MPP39_GPIO,		/* Piggy3 LED[2] */
104 	MPP40_GPIO,		/* Piggy3 LED[3] */
105 	MPP41_GPIO,		/* Piggy3 LED[4] */
106 	MPP42_GPIO,		/* Piggy3 LED[5] */
107 	MPP43_GPIO,		/* Piggy3 LED[6] */
108 	MPP44_GPIO,		/* Piggy3 LED[7], BIST_EN_L */
109 	MPP45_GPIO,		/* Piggy3 LED[8] */
110 	MPP46_GPIO,		/* Reserved */
111 	MPP47_GPIO,		/* Reserved */
112 	MPP48_GPIO,		/* Reserved */
113 	MPP49_GPIO,		/* SW_INTOUTn */
114 	0
115 };
116 
117 #if defined(CONFIG_KM_MGCOGE3UN)
118 /*
119  * Wait for startup OK from mgcoge3ne
120  */
121 int startup_allowed(void)
122 {
123 	unsigned char buf;
124 
125 	/*
126 	 * Read CIRQ16 bit (bit 0)
127 	 */
128 	if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
129 		printf("%s: Error reading Boco\n", __func__);
130 	else
131 		if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
132 			return 1;
133 	return 0;
134 }
135 #endif
136 
137 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
138 /*
139  * All boards with PIGGY4 connected via a simple switch have ethernet always
140  * present.
141  */
142 int ethernet_present(void)
143 {
144 	return 1;
145 }
146 #else
147 int ethernet_present(void)
148 {
149 	uchar	buf;
150 	int	ret = 0;
151 
152 	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
153 		printf("%s: Error reading Boco\n", __func__);
154 		return -1;
155 	}
156 	if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
157 		ret = 1;
158 
159 	return ret;
160 }
161 #endif
162 
163 int initialize_unit_leds(void)
164 {
165 	/*
166 	 * Init the unit LEDs per default they all are
167 	 * ok apart from bootstat
168 	 */
169 	uchar buf;
170 
171 	if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
172 		printf("%s: Error reading Boco\n", __func__);
173 		return -1;
174 	}
175 	buf |= MASK_WRL_UNITRUN;
176 	if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
177 		printf("%s: Error writing Boco\n", __func__);
178 		return -1;
179 	}
180 	return 0;
181 }
182 
183 #if defined(CONFIG_BOOTCOUNT_LIMIT)
184 void set_bootcount_addr(void)
185 {
186 	uchar buf[32];
187 	unsigned int bootcountaddr;
188 	bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
189 	sprintf((char *)buf, "0x%x", bootcountaddr);
190 	setenv("bootcountaddr", (char *)buf);
191 }
192 #endif
193 
194 int misc_init_r(void)
195 {
196 	char *str;
197 	int mach_type;
198 
199 	str = getenv("mach_type");
200 	if (str != NULL) {
201 		mach_type = simple_strtoul(str, NULL, 10);
202 		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
203 		gd->bd->bi_arch_number = mach_type;
204 	}
205 #if defined(CONFIG_KM_MGCOGE3UN)
206 	char *wait_for_ne;
207 	wait_for_ne = getenv("waitforne");
208 	if (wait_for_ne != NULL) {
209 		if (strcmp(wait_for_ne, "true") == 0) {
210 			int cnt = 0;
211 			int abort = 0;
212 			puts("NE go: ");
213 			while (startup_allowed() == 0) {
214 				if (tstc()) {
215 					(void) getc(); /* consume input */
216 					abort = 1;
217 					break;
218 				}
219 				udelay(200000);
220 				cnt++;
221 				if (cnt == 5)
222 					puts("wait\b\b\b\b");
223 				if (cnt == 10) {
224 					cnt = 0;
225 					puts("    \b\b\b\b");
226 				}
227 			}
228 			if (abort == 1)
229 				printf("\nAbort waiting for ne\n");
230 			else
231 				puts("OK\n");
232 		}
233 	}
234 #endif
235 
236 	initialize_unit_leds();
237 	set_km_env();
238 #if defined(CONFIG_BOOTCOUNT_LIMIT)
239 	set_bootcount_addr();
240 #endif
241 	return 0;
242 }
243 
244 int board_early_init_f(void)
245 {
246 #if defined(CONFIG_SOFT_I2C)
247 	u32 tmp;
248 
249 	/* set the 2 bitbang i2c pins as output gpios */
250 	tmp = readl(KW_GPIO0_BASE + 4);
251 	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
252 #endif
253 
254 	kirkwood_mpp_conf(kwmpp_config, NULL);
255 	return 0;
256 }
257 
258 int board_init(void)
259 {
260 	/*
261 	 * arch number of board
262 	 */
263 	gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
264 
265 	/* address of boot parameters */
266 	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
267 
268 	/*
269 	 * The KM_FLASH_GPIO_PIN switches between using a
270 	 * NAND or a SPI FLASH. Set this pin on start
271 	 * to NAND mode.
272 	 */
273 	kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
274 	kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
275 
276 #if defined(CONFIG_SOFT_I2C)
277 	/*
278 	 * Reinit the GPIO for I2C Bitbang driver so that the now
279 	 * available gpio framework is consistent. The calls to
280 	 * direction output in are not necessary, they are already done in
281 	 * board_early_init_f
282 	 */
283 	kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
284 	kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
285 #endif
286 
287 #if defined(CONFIG_SYS_EEPROM_WREN)
288 	kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
289 	kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
290 #endif
291 
292 #if defined(CONFIG_KM_FPGA_CONFIG)
293 	trigger_fpga_config();
294 #endif
295 
296 	return 0;
297 }
298 
299 int board_late_init(void)
300 {
301 #if defined(CONFIG_KMCOGE5UN)
302 /* I/O pin to erase flash RGPP09 = MPP43 */
303 #define KM_FLASH_ERASE_ENABLE	43
304 	u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
305 
306 	/* if pin 1 do full erase */
307 	if (dip_switch != 0) {
308 		/* start bootloader */
309 		puts("DIP:   Enabled\n");
310 		setenv("actual_bank", "0");
311 	}
312 #endif
313 
314 #if defined(CONFIG_KM_FPGA_CONFIG)
315 	wait_for_fpga_config();
316 	fpga_reset();
317 	toggle_eeprom_spi_bus();
318 #endif
319 	return 0;
320 }
321 
322 int board_spi_claim_bus(struct spi_slave *slave)
323 {
324 	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
325 
326 	return 0;
327 }
328 
329 void board_spi_release_bus(struct spi_slave *slave)
330 {
331 	kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
332 }
333 
334 int dram_init(void)
335 {
336 	/* dram_init must store complete ramsize in gd->ram_size */
337 	/* Fix this */
338 	gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
339 				kw_sdram_bs(0));
340 	return 0;
341 }
342 
343 void dram_init_banksize(void)
344 {
345 	int i;
346 
347 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
348 		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
349 		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
350 						       kw_sdram_bs(i));
351 	}
352 }
353 
354 #if (defined(CONFIG_KM_PIGGY4_88E6061))
355 
356 #define	PHY_LED_SEL_REG		0x18
357 #define PHY_LED0_LINK		(0x5)
358 #define PHY_LED1_ACT		(0x8<<4)
359 #define PHY_LED2_INT		(0xe<<8)
360 #define	PHY_SPEC_CTRL_REG	0x1c
361 #define PHY_RGMII_CLK_STABLE	(0x1<<10)
362 #define PHY_CLSA		(0x1<<1)
363 
364 /* Configure and enable MV88E3018 PHY */
365 void reset_phy(void)
366 {
367 	char *name = "egiga0";
368 	unsigned short reg;
369 
370 	if (miiphy_set_current_dev(name))
371 		return;
372 
373 	/* RGMII clk transition on data stable */
374 	if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
375 		printf("Error reading PHY spec ctrl reg\n");
376 	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
377 		reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
378 		printf("Error writing PHY spec ctrl reg\n");
379 
380 	/* leds setup */
381 	if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
382 		PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
383 		printf("Error writing PHY LED reg\n");
384 
385 	/* reset the phy */
386 	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
387 }
388 #else
389 /* Configure and enable MV88E1118 PHY on the piggy*/
390 void reset_phy(void)
391 {
392 	char *name = "egiga0";
393 
394 	if (miiphy_set_current_dev(name))
395 		return;
396 
397 	/* reset the phy */
398 	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
399 }
400 #endif
401 
402 
403 #if defined(CONFIG_HUSH_INIT_VAR)
404 int hush_init_var(void)
405 {
406 	ivm_read_eeprom();
407 	return 0;
408 }
409 #endif
410 
411 #if defined(CONFIG_SOFT_I2C)
412 void set_sda(int state)
413 {
414 	I2C_ACTIVE;
415 	I2C_SDA(state);
416 }
417 
418 void set_scl(int state)
419 {
420 	I2C_SCL(state);
421 }
422 
423 int get_sda(void)
424 {
425 	I2C_TRISTATE;
426 	return I2C_READ;
427 }
428 
429 int get_scl(void)
430 {
431 	return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
432 }
433 #endif
434 
435 #if defined(CONFIG_POST)
436 
437 #define KM_POST_EN_L	44
438 #define POST_WORD_OFF	8
439 
440 int post_hotkeys_pressed(void)
441 {
442 #if defined(CONFIG_KM_COGE5UN)
443 	return kw_gpio_get_value(KM_POST_EN_L);
444 #else
445 	return !kw_gpio_get_value(KM_POST_EN_L);
446 #endif
447 }
448 
449 ulong post_word_load(void)
450 {
451 	void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
452 	return in_le32(addr);
453 
454 }
455 void post_word_store(ulong value)
456 {
457 	void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
458 	out_le32(addr, value);
459 }
460 
461 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
462 {
463 	*vstart = CONFIG_SYS_SDRAM_BASE;
464 
465 	/* we go up to relocation plus a 1 MB margin */
466 	*size = CONFIG_SYS_TEXT_BASE - (1<<20);
467 
468 	return 0;
469 }
470 #endif
471 
472 #if defined(CONFIG_SYS_EEPROM_WREN)
473 int eeprom_write_enable(unsigned dev_addr, int state)
474 {
475 	kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
476 
477 	return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
478 }
479 #endif
480