1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <i2c.h> 33 #include <nand.h> 34 #include <netdev.h> 35 #include <miiphy.h> 36 #include <spi.h> 37 #include <asm/io.h> 38 #include <asm/arch/cpu.h> 39 #include <asm/arch/kirkwood.h> 40 #include <asm/arch/mpp.h> 41 42 #include "../common/common.h" 43 44 DECLARE_GLOBAL_DATA_PTR; 45 46 /* 47 * BOCO FPGA definitions 48 */ 49 #define BOCO 0x10 50 #define REG_CTRL_H 0x02 51 #define MASK_WRL_UNITRUN 0x01 52 #define MASK_RBX_PGY_PRESENT 0x40 53 #define REG_IRQ_CIRQ2 0x2d 54 #define MASK_RBI_DEFECT_16 0x01 55 56 /* Multi-Purpose Pins Functionality configuration */ 57 static const u32 kwmpp_config[] = { 58 MPP0_NF_IO2, 59 MPP1_NF_IO3, 60 MPP2_NF_IO4, 61 MPP3_NF_IO5, 62 MPP4_NF_IO6, 63 MPP5_NF_IO7, 64 MPP6_SYSRST_OUTn, 65 MPP7_PEX_RST_OUTn, 66 #if defined(CONFIG_SOFT_I2C) 67 MPP8_GPIO, /* SDA */ 68 MPP9_GPIO, /* SCL */ 69 #endif 70 #if defined(CONFIG_HARD_I2C) 71 MPP8_TW_SDA, 72 MPP9_TW_SCK, 73 #endif 74 MPP10_UART0_TXD, 75 MPP11_UART0_RXD, 76 MPP12_GPO, /* Reserved */ 77 MPP13_UART1_TXD, 78 MPP14_UART1_RXD, 79 MPP15_GPIO, /* Not used */ 80 MPP16_GPIO, /* Not used */ 81 MPP17_GPIO, /* Reserved */ 82 MPP18_NF_IO0, 83 MPP19_NF_IO1, 84 MPP20_GPIO, 85 MPP21_GPIO, 86 MPP22_GPIO, 87 MPP23_GPIO, 88 MPP24_GPIO, 89 MPP25_GPIO, 90 MPP26_GPIO, 91 MPP27_GPIO, 92 MPP28_GPIO, 93 MPP29_GPIO, 94 MPP30_GPIO, 95 MPP31_GPIO, 96 MPP32_GPIO, 97 MPP33_GPIO, 98 MPP34_GPIO, /* CDL1 (input) */ 99 MPP35_GPIO, /* CDL2 (input) */ 100 MPP36_GPIO, /* MAIN_IRQ (input) */ 101 MPP37_GPIO, /* BOARD_LED */ 102 MPP38_GPIO, /* Piggy3 LED[1] */ 103 MPP39_GPIO, /* Piggy3 LED[2] */ 104 MPP40_GPIO, /* Piggy3 LED[3] */ 105 MPP41_GPIO, /* Piggy3 LED[4] */ 106 MPP42_GPIO, /* Piggy3 LED[5] */ 107 MPP43_GPIO, /* Piggy3 LED[6] */ 108 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 109 MPP45_GPIO, /* Piggy3 LED[8] */ 110 MPP46_GPIO, /* Reserved */ 111 MPP47_GPIO, /* Reserved */ 112 MPP48_GPIO, /* Reserved */ 113 MPP49_GPIO, /* SW_INTOUTn */ 114 0 115 }; 116 117 #if defined(CONFIG_KM_MGCOGE3UN) 118 /* 119 * Wait for startup OK from mgcoge3ne 120 */ 121 int startup_allowed(void) 122 { 123 unsigned char buf; 124 125 /* 126 * Read CIRQ16 bit (bit 0) 127 */ 128 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 129 printf("%s: Error reading Boco\n", __func__); 130 else 131 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 132 return 1; 133 return 0; 134 } 135 #endif 136 137 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 138 /* 139 * All boards with PIGGY4 connected via a simple switch have ethernet always 140 * present. 141 */ 142 int ethernet_present(void) 143 { 144 return 1; 145 } 146 #else 147 int ethernet_present(void) 148 { 149 uchar buf; 150 int ret = 0; 151 152 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 153 printf("%s: Error reading Boco\n", __func__); 154 return -1; 155 } 156 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 157 ret = 1; 158 159 return ret; 160 } 161 #endif 162 163 int initialize_unit_leds(void) 164 { 165 /* 166 * Init the unit LEDs per default they all are 167 * ok apart from bootstat 168 */ 169 uchar buf; 170 171 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 172 printf("%s: Error reading Boco\n", __func__); 173 return -1; 174 } 175 buf |= MASK_WRL_UNITRUN; 176 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 177 printf("%s: Error writing Boco\n", __func__); 178 return -1; 179 } 180 return 0; 181 } 182 183 #if defined(CONFIG_BOOTCOUNT_LIMIT) 184 void set_bootcount_addr(void) 185 { 186 uchar buf[32]; 187 unsigned int bootcountaddr; 188 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 189 sprintf((char *)buf, "0x%x", bootcountaddr); 190 setenv("bootcountaddr", (char *)buf); 191 } 192 #endif 193 194 int misc_init_r(void) 195 { 196 #if defined(CONFIG_KM_MGCOGE3UN) 197 char *wait_for_ne; 198 wait_for_ne = getenv("waitforne"); 199 if (wait_for_ne != NULL) { 200 if (strcmp(wait_for_ne, "true") == 0) { 201 int cnt = 0; 202 int abort = 0; 203 puts("NE go: "); 204 while (startup_allowed() == 0) { 205 if (tstc()) { 206 (void) getc(); /* consume input */ 207 abort = 1; 208 break; 209 } 210 udelay(200000); 211 cnt++; 212 if (cnt == 5) 213 puts("wait\b\b\b\b"); 214 if (cnt == 10) { 215 cnt = 0; 216 puts(" \b\b\b\b"); 217 } 218 } 219 if (abort == 1) 220 printf("\nAbort waiting for ne\n"); 221 else 222 puts("OK\n"); 223 } 224 } 225 #endif 226 227 initialize_unit_leds(); 228 set_km_env(); 229 #if defined(CONFIG_BOOTCOUNT_LIMIT) 230 set_bootcount_addr(); 231 #endif 232 return 0; 233 } 234 235 int board_early_init_f(void) 236 { 237 #if defined(CONFIG_SOFT_I2C) 238 u32 tmp; 239 240 /* set the 2 bitbang i2c pins as output gpios */ 241 tmp = readl(KW_GPIO0_BASE + 4); 242 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); 243 #endif 244 /* adjust SDRAM size for bank 0 */ 245 kw_sdram_size_adjust(0); 246 kirkwood_mpp_conf(kwmpp_config, NULL); 247 return 0; 248 } 249 250 int board_init(void) 251 { 252 /* address of boot parameters */ 253 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 254 255 /* 256 * The KM_FLASH_GPIO_PIN switches between using a 257 * NAND or a SPI FLASH. Set this pin on start 258 * to NAND mode. 259 */ 260 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 261 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 262 263 #if defined(CONFIG_SOFT_I2C) 264 /* 265 * Reinit the GPIO for I2C Bitbang driver so that the now 266 * available gpio framework is consistent. The calls to 267 * direction output in are not necessary, they are already done in 268 * board_early_init_f 269 */ 270 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 271 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 272 #endif 273 274 #if defined(CONFIG_SYS_EEPROM_WREN) 275 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 276 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 277 #endif 278 279 #if defined(CONFIG_KM_FPGA_CONFIG) 280 trigger_fpga_config(); 281 #endif 282 283 return 0; 284 } 285 286 int board_late_init(void) 287 { 288 #if defined(CONFIG_KMCOGE5UN) 289 /* I/O pin to erase flash RGPP09 = MPP43 */ 290 #define KM_FLASH_ERASE_ENABLE 43 291 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 292 293 /* if pin 1 do full erase */ 294 if (dip_switch != 0) { 295 /* start bootloader */ 296 puts("DIP: Enabled\n"); 297 setenv("actual_bank", "0"); 298 } 299 #endif 300 301 #if defined(CONFIG_KM_FPGA_CONFIG) 302 wait_for_fpga_config(); 303 fpga_reset(); 304 toggle_eeprom_spi_bus(); 305 #endif 306 return 0; 307 } 308 309 int board_spi_claim_bus(struct spi_slave *slave) 310 { 311 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 312 313 return 0; 314 } 315 316 void board_spi_release_bus(struct spi_slave *slave) 317 { 318 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 319 } 320 321 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 322 323 #define PHY_LED_SEL_REG 0x18 324 #define PHY_LED0_LINK (0x5) 325 #define PHY_LED1_ACT (0x8<<4) 326 #define PHY_LED2_INT (0xe<<8) 327 #define PHY_SPEC_CTRL_REG 0x1c 328 #define PHY_RGMII_CLK_STABLE (0x1<<10) 329 #define PHY_CLSA (0x1<<1) 330 331 /* Configure and enable MV88E3018 PHY */ 332 void reset_phy(void) 333 { 334 char *name = "egiga0"; 335 unsigned short reg; 336 337 if (miiphy_set_current_dev(name)) 338 return; 339 340 /* RGMII clk transition on data stable */ 341 if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 342 printf("Error reading PHY spec ctrl reg\n"); 343 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 344 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 345 printf("Error writing PHY spec ctrl reg\n"); 346 347 /* leds setup */ 348 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 349 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 350 printf("Error writing PHY LED reg\n"); 351 352 /* reset the phy */ 353 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 354 } 355 #elif defined(CONFIG_KM_PIGGY4_88E6352) 356 357 #include <mv88e6352.h> 358 359 #if defined(CONFIG_KM_NUSA) 360 struct mv88e_sw_reg extsw_conf[] = { 361 /* 362 * port 0, PIGGY4, autoneg 363 * first the fix for the 1000Mbits Autoneg, this is from 364 * a Marvell errata, the regs are undocumented 365 */ 366 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 367 { PHY(0), PHY_STATUS, AN1000FIX }, 368 { PHY(0), PHY_PAGE, 0 }, 369 /* now the real port and phy configuration */ 370 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 371 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 372 { PHY(0), PHY_1000_CTRL, NO_ADV }, 373 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 374 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 375 FULL_DUPLEX }, 376 /* port 1, unused */ 377 { PORT(1), PORT_CTRL, PORT_DIS }, 378 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 379 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 380 /* port 2, unused */ 381 { PORT(2), PORT_CTRL, PORT_DIS }, 382 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 383 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 384 /* port 3, unused */ 385 { PORT(3), PORT_CTRL, PORT_DIS }, 386 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 387 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 388 /* port 4, ICNEV, SerDes, SGMII */ 389 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 390 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 391 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 392 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 393 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 394 /* port 5, CPU_RGMII */ 395 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 396 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 397 FULL_DPX_FOR | SPEED_1000_FOR }, 398 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 399 /* port 6, unused, this port has no phy */ 400 { PORT(6), PORT_CTRL, PORT_DIS }, 401 }; 402 #else 403 struct mv88e_sw_reg extsw_conf[] = {}; 404 #endif 405 406 void reset_phy(void) 407 { 408 #if defined(CONFIG_KM_MVEXTSW_ADDR) 409 char *name = "egiga0"; 410 411 if (miiphy_set_current_dev(name)) 412 return; 413 414 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 415 ARRAY_SIZE(extsw_conf)); 416 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 417 #endif 418 } 419 420 #else 421 /* Configure and enable MV88E1118 PHY on the piggy*/ 422 void reset_phy(void) 423 { 424 char *name = "egiga0"; 425 426 if (miiphy_set_current_dev(name)) 427 return; 428 429 /* reset the phy */ 430 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 431 } 432 #endif 433 434 435 #if defined(CONFIG_HUSH_INIT_VAR) 436 int hush_init_var(void) 437 { 438 ivm_read_eeprom(); 439 return 0; 440 } 441 #endif 442 443 #if defined(CONFIG_SOFT_I2C) 444 void set_sda(int state) 445 { 446 I2C_ACTIVE; 447 I2C_SDA(state); 448 } 449 450 void set_scl(int state) 451 { 452 I2C_SCL(state); 453 } 454 455 int get_sda(void) 456 { 457 I2C_TRISTATE; 458 return I2C_READ; 459 } 460 461 int get_scl(void) 462 { 463 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 464 } 465 #endif 466 467 #if defined(CONFIG_POST) 468 469 #define KM_POST_EN_L 44 470 #define POST_WORD_OFF 8 471 472 int post_hotkeys_pressed(void) 473 { 474 #if defined(CONFIG_KM_COGE5UN) 475 return kw_gpio_get_value(KM_POST_EN_L); 476 #else 477 return !kw_gpio_get_value(KM_POST_EN_L); 478 #endif 479 } 480 481 ulong post_word_load(void) 482 { 483 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 484 return in_le32(addr); 485 486 } 487 void post_word_store(ulong value) 488 { 489 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 490 out_le32(addr, value); 491 } 492 493 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 494 { 495 *vstart = CONFIG_SYS_SDRAM_BASE; 496 497 /* we go up to relocation plus a 1 MB margin */ 498 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 499 500 return 0; 501 } 502 #endif 503 504 #if defined(CONFIG_SYS_EEPROM_WREN) 505 int eeprom_write_enable(unsigned dev_addr, int state) 506 { 507 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 508 509 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 510 } 511 #endif 512