1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <nand.h> 18 #include <netdev.h> 19 #include <miiphy.h> 20 #include <spi.h> 21 #include <asm/io.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/soc.h> 24 #include <asm/arch/mpp.h> 25 26 #include "../common/common.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * BOCO FPGA definitions 32 */ 33 #define BOCO 0x10 34 #define REG_CTRL_H 0x02 35 #define MASK_WRL_UNITRUN 0x01 36 #define MASK_RBX_PGY_PRESENT 0x40 37 #define REG_IRQ_CIRQ2 0x2d 38 #define MASK_RBI_DEFECT_16 0x01 39 40 /* Multi-Purpose Pins Functionality configuration */ 41 static const u32 kwmpp_config[] = { 42 MPP0_NF_IO2, 43 MPP1_NF_IO3, 44 MPP2_NF_IO4, 45 MPP3_NF_IO5, 46 MPP4_NF_IO6, 47 MPP5_NF_IO7, 48 MPP6_SYSRST_OUTn, 49 #if defined(KM_PCIE_RESET_MPP7) 50 MPP7_GPO, 51 #else 52 MPP7_PEX_RST_OUTn, 53 #endif 54 #if defined(CONFIG_SYS_I2C_SOFT) 55 MPP8_GPIO, /* SDA */ 56 MPP9_GPIO, /* SCL */ 57 #endif 58 #if defined(CONFIG_HARD_I2C) 59 MPP8_TW_SDA, 60 MPP9_TW_SCK, 61 #endif 62 MPP10_UART0_TXD, 63 MPP11_UART0_RXD, 64 MPP12_GPO, /* Reserved */ 65 MPP13_UART1_TXD, 66 MPP14_UART1_RXD, 67 MPP15_GPIO, /* Not used */ 68 MPP16_GPIO, /* Not used */ 69 MPP17_GPIO, /* Reserved */ 70 MPP18_NF_IO0, 71 MPP19_NF_IO1, 72 MPP20_GPIO, 73 MPP21_GPIO, 74 MPP22_GPIO, 75 MPP23_GPIO, 76 MPP24_GPIO, 77 MPP25_GPIO, 78 MPP26_GPIO, 79 MPP27_GPIO, 80 MPP28_GPIO, 81 MPP29_GPIO, 82 MPP30_GPIO, 83 MPP31_GPIO, 84 MPP32_GPIO, 85 MPP33_GPIO, 86 MPP34_GPIO, /* CDL1 (input) */ 87 MPP35_GPIO, /* CDL2 (input) */ 88 MPP36_GPIO, /* MAIN_IRQ (input) */ 89 MPP37_GPIO, /* BOARD_LED */ 90 MPP38_GPIO, /* Piggy3 LED[1] */ 91 MPP39_GPIO, /* Piggy3 LED[2] */ 92 MPP40_GPIO, /* Piggy3 LED[3] */ 93 MPP41_GPIO, /* Piggy3 LED[4] */ 94 MPP42_GPIO, /* Piggy3 LED[5] */ 95 MPP43_GPIO, /* Piggy3 LED[6] */ 96 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 97 MPP45_GPIO, /* Piggy3 LED[8] */ 98 MPP46_GPIO, /* Reserved */ 99 MPP47_GPIO, /* Reserved */ 100 MPP48_GPIO, /* Reserved */ 101 MPP49_GPIO, /* SW_INTOUTn */ 102 0 103 }; 104 105 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; 106 107 #if defined(CONFIG_KM_MGCOGE3UN) 108 /* 109 * Wait for startup OK from mgcoge3ne 110 */ 111 static int startup_allowed(void) 112 { 113 unsigned char buf; 114 115 /* 116 * Read CIRQ16 bit (bit 0) 117 */ 118 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 119 printf("%s: Error reading Boco\n", __func__); 120 else 121 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 122 return 1; 123 return 0; 124 } 125 #endif 126 127 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) 128 /* 129 * All boards with PIGGY4 connected via a simple switch have ethernet always 130 * present. 131 */ 132 int ethernet_present(void) 133 { 134 return 1; 135 } 136 #else 137 int ethernet_present(void) 138 { 139 uchar buf; 140 int ret = 0; 141 142 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 143 printf("%s: Error reading Boco\n", __func__); 144 return -1; 145 } 146 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 147 ret = 1; 148 149 return ret; 150 } 151 #endif 152 153 static int initialize_unit_leds(void) 154 { 155 /* 156 * Init the unit LEDs per default they all are 157 * ok apart from bootstat 158 */ 159 uchar buf; 160 161 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 162 printf("%s: Error reading Boco\n", __func__); 163 return -1; 164 } 165 buf |= MASK_WRL_UNITRUN; 166 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 167 printf("%s: Error writing Boco\n", __func__); 168 return -1; 169 } 170 return 0; 171 } 172 173 static void set_bootcount_addr(void) 174 { 175 uchar buf[32]; 176 unsigned int bootcountaddr; 177 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 178 sprintf((char *)buf, "0x%x", bootcountaddr); 179 setenv("bootcountaddr", (char *)buf); 180 } 181 182 int misc_init_r(void) 183 { 184 #if defined(CONFIG_KM_MGCOGE3UN) 185 char *wait_for_ne; 186 wait_for_ne = getenv("waitforne"); 187 if (wait_for_ne != NULL) { 188 if (strcmp(wait_for_ne, "true") == 0) { 189 int cnt = 0; 190 int abort = 0; 191 puts("NE go: "); 192 while (startup_allowed() == 0) { 193 if (tstc()) { 194 (void) getc(); /* consume input */ 195 abort = 1; 196 break; 197 } 198 udelay(200000); 199 cnt++; 200 if (cnt == 5) 201 puts("wait\b\b\b\b"); 202 if (cnt == 10) { 203 cnt = 0; 204 puts(" \b\b\b\b"); 205 } 206 } 207 if (abort == 1) 208 printf("\nAbort waiting for ne\n"); 209 else 210 puts("OK\n"); 211 } 212 } 213 #endif 214 215 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 216 217 initialize_unit_leds(); 218 set_km_env(); 219 set_bootcount_addr(); 220 return 0; 221 } 222 223 int board_early_init_f(void) 224 { 225 #if defined(CONFIG_SYS_I2C_SOFT) 226 u32 tmp; 227 228 /* set the 2 bitbang i2c pins as output gpios */ 229 tmp = readl(MVEBU_GPIO0_BASE + 4); 230 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4); 231 #endif 232 /* adjust SDRAM size for bank 0 */ 233 mvebu_sdram_size_adjust(0); 234 kirkwood_mpp_conf(kwmpp_config, NULL); 235 return 0; 236 } 237 238 int board_init(void) 239 { 240 /* address of boot parameters */ 241 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 242 243 /* 244 * The KM_FLASH_GPIO_PIN switches between using a 245 * NAND or a SPI FLASH. Set this pin on start 246 * to NAND mode. 247 */ 248 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); 249 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); 250 251 #if defined(CONFIG_SYS_I2C_SOFT) 252 /* 253 * Reinit the GPIO for I2C Bitbang driver so that the now 254 * available gpio framework is consistent. The calls to 255 * direction output in are not necessary, they are already done in 256 * board_early_init_f 257 */ 258 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 259 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 260 #endif 261 262 #if defined(CONFIG_SYS_EEPROM_WREN) 263 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 264 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 265 #endif 266 267 #if defined(CONFIG_KM_FPGA_CONFIG) 268 trigger_fpga_config(); 269 #endif 270 271 return 0; 272 } 273 274 int board_late_init(void) 275 { 276 #if defined(CONFIG_KMCOGE5UN) 277 /* I/O pin to erase flash RGPP09 = MPP43 */ 278 #define KM_FLASH_ERASE_ENABLE 43 279 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); 280 281 /* if pin 1 do full erase */ 282 if (dip_switch != 0) { 283 /* start bootloader */ 284 puts("DIP: Enabled\n"); 285 setenv("actual_bank", "0"); 286 } 287 #endif 288 289 #if defined(CONFIG_KM_FPGA_CONFIG) 290 wait_for_fpga_config(); 291 fpga_reset(); 292 toggle_eeprom_spi_bus(); 293 #endif 294 return 0; 295 } 296 297 int board_spi_claim_bus(struct spi_slave *slave) 298 { 299 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); 300 301 return 0; 302 } 303 304 void board_spi_release_bus(struct spi_slave *slave) 305 { 306 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); 307 } 308 309 #if (defined(CONFIG_KM_PIGGY4_88E6061)) 310 311 #define PHY_LED_SEL_REG 0x18 312 #define PHY_LED0_LINK (0x5) 313 #define PHY_LED1_ACT (0x8<<4) 314 #define PHY_LED2_INT (0xe<<8) 315 #define PHY_SPEC_CTRL_REG 0x1c 316 #define PHY_RGMII_CLK_STABLE (0x1<<10) 317 #define PHY_CLSA (0x1<<1) 318 319 /* Configure and enable MV88E3018 PHY */ 320 void reset_phy(void) 321 { 322 char *name = "egiga0"; 323 unsigned short reg; 324 325 if (miiphy_set_current_dev(name)) 326 return; 327 328 /* RGMII clk transition on data stable */ 329 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) 330 printf("Error reading PHY spec ctrl reg\n"); 331 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, 332 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) 333 printf("Error writing PHY spec ctrl reg\n"); 334 335 /* leds setup */ 336 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, 337 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) 338 printf("Error writing PHY LED reg\n"); 339 340 /* reset the phy */ 341 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 342 } 343 #elif defined(CONFIG_KM_PIGGY4_88E6352) 344 345 #include <mv88e6352.h> 346 347 #if defined(CONFIG_KM_NUSA) 348 struct mv88e_sw_reg extsw_conf[] = { 349 /* 350 * port 0, PIGGY4, autoneg 351 * first the fix for the 1000Mbits Autoneg, this is from 352 * a Marvell errata, the regs are undocumented 353 */ 354 { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, 355 { PHY(0), PHY_STATUS, AN1000FIX }, 356 { PHY(0), PHY_PAGE, 0 }, 357 /* now the real port and phy configuration */ 358 { PORT(0), PORT_PHY, NO_SPEED_FOR }, 359 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 360 { PHY(0), PHY_1000_CTRL, NO_ADV }, 361 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 362 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 363 FULL_DUPLEX }, 364 /* port 1, unused */ 365 { PORT(1), PORT_CTRL, PORT_DIS }, 366 { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, 367 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 368 /* port 2, unused */ 369 { PORT(2), PORT_CTRL, PORT_DIS }, 370 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 371 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 372 /* port 3, unused */ 373 { PORT(3), PORT_CTRL, PORT_DIS }, 374 { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, 375 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 376 /* port 4, ICNEV, SerDes, SGMII */ 377 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 378 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 379 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 380 { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, 381 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 382 /* port 5, CPU_RGMII */ 383 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | 384 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | 385 FULL_DPX_FOR | SPEED_1000_FOR }, 386 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 387 /* port 6, unused, this port has no phy */ 388 { PORT(6), PORT_CTRL, PORT_DIS }, 389 }; 390 #else 391 struct mv88e_sw_reg extsw_conf[] = {}; 392 #endif 393 394 void reset_phy(void) 395 { 396 #if defined(CONFIG_KM_MVEXTSW_ADDR) 397 char *name = "egiga0"; 398 399 if (miiphy_set_current_dev(name)) 400 return; 401 402 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 403 ARRAY_SIZE(extsw_conf)); 404 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 405 #endif 406 } 407 408 #else 409 /* Configure and enable MV88E1118 PHY on the piggy*/ 410 void reset_phy(void) 411 { 412 char *name = "egiga0"; 413 414 if (miiphy_set_current_dev(name)) 415 return; 416 417 /* reset the phy */ 418 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 419 } 420 #endif 421 422 423 #if defined(CONFIG_HUSH_INIT_VAR) 424 int hush_init_var(void) 425 { 426 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 427 return 0; 428 } 429 #endif 430 431 #if defined(CONFIG_SYS_I2C_SOFT) 432 void set_sda(int state) 433 { 434 I2C_ACTIVE; 435 I2C_SDA(state); 436 } 437 438 void set_scl(int state) 439 { 440 I2C_SCL(state); 441 } 442 443 int get_sda(void) 444 { 445 I2C_TRISTATE; 446 return I2C_READ; 447 } 448 449 int get_scl(void) 450 { 451 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 452 } 453 #endif 454 455 #if defined(CONFIG_POST) 456 457 #define KM_POST_EN_L 44 458 #define POST_WORD_OFF 8 459 460 int post_hotkeys_pressed(void) 461 { 462 #if defined(CONFIG_KM_COGE5UN) 463 return kw_gpio_get_value(KM_POST_EN_L); 464 #else 465 return !kw_gpio_get_value(KM_POST_EN_L); 466 #endif 467 } 468 469 ulong post_word_load(void) 470 { 471 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 472 return in_le32(addr); 473 474 } 475 void post_word_store(ulong value) 476 { 477 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); 478 out_le32(addr, value); 479 } 480 481 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 482 { 483 *vstart = CONFIG_SYS_SDRAM_BASE; 484 485 /* we go up to relocation plus a 1 MB margin */ 486 *size = CONFIG_SYS_TEXT_BASE - (1<<20); 487 488 return 0; 489 } 490 #endif 491 492 #if defined(CONFIG_SYS_EEPROM_WREN) 493 int eeprom_write_enable(unsigned dev_addr, int state) 494 { 495 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 496 497 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 498 } 499 #endif 500