1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2009 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * (C) Copyright 2010 10 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 28 * MA 02110-1301 USA 29 */ 30 31 #include <common.h> 32 #include <i2c.h> 33 #include <nand.h> 34 #include <netdev.h> 35 #include <miiphy.h> 36 #include <asm/io.h> 37 #include <asm/arch/kirkwood.h> 38 #include <asm/arch/mpp.h> 39 40 #include "../common/common.h" 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* 45 * BOCO FPGA definitions 46 */ 47 #define BOCO 0x10 48 #define REG_CTRL_H 0x02 49 #define MASK_WRL_UNITRUN 0x01 50 #define MASK_RBX_PGY_PRESENT 0x40 51 #define REG_IRQ_CIRQ2 0x2d 52 #define MASK_RBI_DEFECT_16 0x01 53 54 /* Multi-Purpose Pins Functionality configuration */ 55 u32 kwmpp_config[] = { 56 MPP0_NF_IO2, 57 MPP1_NF_IO3, 58 MPP2_NF_IO4, 59 MPP3_NF_IO5, 60 MPP4_NF_IO6, 61 MPP5_NF_IO7, 62 MPP6_SYSRST_OUTn, 63 MPP7_PEX_RST_OUTn, 64 #if defined(CONFIG_SOFT_I2C) 65 MPP8_GPIO, /* SDA */ 66 MPP9_GPIO, /* SCL */ 67 #endif 68 #if defined(CONFIG_HARD_I2C) 69 MPP8_TW_SDA, 70 MPP9_TW_SCK, 71 #endif 72 MPP10_UART0_TXD, 73 MPP11_UART0_RXD, 74 MPP12_GPO, /* Reserved */ 75 MPP13_UART1_TXD, 76 MPP14_UART1_RXD, 77 MPP15_GPIO, /* Not used */ 78 MPP16_GPIO, /* Not used */ 79 MPP17_GPIO, /* Reserved */ 80 MPP18_NF_IO0, 81 MPP19_NF_IO1, 82 MPP20_GPIO, 83 MPP21_GPIO, 84 MPP22_GPIO, 85 MPP23_GPIO, 86 MPP24_GPIO, 87 MPP25_GPIO, 88 MPP26_GPIO, 89 MPP27_GPIO, 90 MPP28_GPIO, 91 MPP29_GPIO, 92 MPP30_GPIO, 93 MPP31_GPIO, 94 MPP32_GPIO, 95 MPP33_GPIO, 96 MPP34_GPIO, /* CDL1 (input) */ 97 MPP35_GPIO, /* CDL2 (input) */ 98 MPP36_GPIO, /* MAIN_IRQ (input) */ 99 MPP37_GPIO, /* BOARD_LED */ 100 MPP38_GPIO, /* Piggy3 LED[1] */ 101 MPP39_GPIO, /* Piggy3 LED[2] */ 102 MPP40_GPIO, /* Piggy3 LED[3] */ 103 MPP41_GPIO, /* Piggy3 LED[4] */ 104 MPP42_GPIO, /* Piggy3 LED[5] */ 105 MPP43_GPIO, /* Piggy3 LED[6] */ 106 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ 107 MPP45_GPIO, /* Piggy3 LED[8] */ 108 MPP46_GPIO, /* Reserved */ 109 MPP47_GPIO, /* Reserved */ 110 MPP48_GPIO, /* Reserved */ 111 MPP49_GPIO, /* SW_INTOUTn */ 112 0 113 }; 114 115 #if defined(CONFIG_MGCOGE3UN) 116 /* 117 * Wait for startup OK from mgcoge3ne 118 */ 119 int startup_allowed(void) 120 { 121 unsigned char buf; 122 123 /* 124 * Read CIRQ16 bit (bit 0) 125 */ 126 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) 127 printf("%s: Error reading Boco\n", __func__); 128 else 129 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) 130 return 1; 131 return 0; 132 } 133 #endif 134 135 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) 136 /* 137 * These two boards have always ethernet present. Its connected to the mv 138 * switch. 139 */ 140 int ethernet_present(void) 141 { 142 return 1; 143 } 144 #else 145 int ethernet_present(void) 146 { 147 uchar buf; 148 int ret = 0; 149 150 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 151 printf("%s: Error reading Boco\n", __func__); 152 return -1; 153 } 154 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) 155 ret = 1; 156 157 return ret; 158 } 159 #endif 160 161 int initialize_unit_leds(void) 162 { 163 /* 164 * Init the unit LEDs per default they all are 165 * ok apart from bootstat 166 */ 167 uchar buf; 168 169 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 170 printf("%s: Error reading Boco\n", __func__); 171 return -1; 172 } 173 buf |= MASK_WRL_UNITRUN; 174 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { 175 printf("%s: Error writing Boco\n", __func__); 176 return -1; 177 } 178 return 0; 179 } 180 181 #if defined(CONFIG_BOOTCOUNT_LIMIT) 182 void set_bootcount_addr(void) 183 { 184 uchar buf[32]; 185 unsigned int bootcountaddr; 186 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; 187 sprintf((char *)buf, "0x%x", bootcountaddr); 188 setenv("bootcountaddr", (char *)buf); 189 } 190 #endif 191 192 int misc_init_r(void) 193 { 194 char *str; 195 int mach_type; 196 197 str = getenv("mach_type"); 198 if (str != NULL) { 199 mach_type = simple_strtoul(str, NULL, 10); 200 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); 201 gd->bd->bi_arch_number = mach_type; 202 } 203 #if defined(CONFIG_MGCOGE3UN) 204 char *wait_for_ne; 205 wait_for_ne = getenv("waitforne"); 206 if (wait_for_ne != NULL) { 207 if (strcmp(wait_for_ne, "true") == 0) { 208 int cnt = 0; 209 puts("NE go: "); 210 while (startup_allowed() == 0) { 211 udelay(200000); 212 cnt++; 213 if (cnt == 5) 214 puts("wait\b\b\b\b"); 215 if (cnt == 10) { 216 cnt = 0; 217 puts(" \b\b\b\b"); 218 } 219 } 220 puts("OK\n"); 221 } 222 } 223 #endif 224 225 initialize_unit_leds(); 226 set_km_env(); 227 #if defined(CONFIG_BOOTCOUNT_LIMIT) 228 set_bootcount_addr(); 229 #endif 230 return 0; 231 } 232 233 int board_early_init_f(void) 234 { 235 u32 tmp; 236 237 kirkwood_mpp_conf(kwmpp_config); 238 239 /* 240 * The FLASH_GPIO_PIN switches between using a 241 * NAND or a SPI FLASH. Set this pin on start 242 * to NAND mode. 243 */ 244 tmp = readl(KW_GPIO0_BASE); 245 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 246 tmp = readl(KW_GPIO0_BASE + 4); 247 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); 248 249 #if defined(CONFIG_SOFT_I2C) 250 /* init the GPIO for I2C Bitbang driver */ 251 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); 252 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); 253 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); 254 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); 255 #endif 256 #if defined(CONFIG_SYS_EEPROM_WREN) 257 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); 258 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); 259 #endif 260 261 return 0; 262 } 263 264 int board_init(void) 265 { 266 /* 267 * arch number of board 268 */ 269 gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; 270 271 /* address of boot parameters */ 272 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; 273 274 return 0; 275 } 276 277 #if defined(CONFIG_CMD_SF) 278 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 279 { 280 u32 tmp; 281 if (argc < 2) 282 return cmd_usage(cmdtp); 283 284 if ((strcmp(argv[1], "off") == 0)) { 285 printf("SPI FLASH disabled, NAND enabled\n"); 286 /* Multi-Purpose Pins Functionality configuration */ 287 kwmpp_config[0] = MPP0_NF_IO2; 288 kwmpp_config[1] = MPP1_NF_IO3; 289 kwmpp_config[2] = MPP2_NF_IO4; 290 kwmpp_config[3] = MPP3_NF_IO5; 291 292 kirkwood_mpp_conf(kwmpp_config); 293 tmp = readl(KW_GPIO0_BASE); 294 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); 295 } else if ((strcmp(argv[1], "on") == 0)) { 296 printf("SPI FLASH enabled, NAND disabled\n"); 297 /* Multi-Purpose Pins Functionality configuration */ 298 kwmpp_config[0] = MPP0_SPI_SCn; 299 kwmpp_config[1] = MPP1_SPI_MOSI; 300 kwmpp_config[2] = MPP2_SPI_SCK; 301 kwmpp_config[3] = MPP3_SPI_MISO; 302 303 kirkwood_mpp_conf(kwmpp_config); 304 tmp = readl(KW_GPIO0_BASE); 305 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); 306 } else { 307 return cmd_usage(cmdtp); 308 } 309 310 return 0; 311 } 312 313 U_BOOT_CMD( 314 spitoggle, 2, 0, do_spi_toggle, 315 "En-/disable SPI FLASH access", 316 "<on|off> - Enable (on) or disable (off) SPI FLASH access\n" 317 ); 318 #endif 319 320 int dram_init(void) 321 { 322 /* dram_init must store complete ramsize in gd->ram_size */ 323 /* Fix this */ 324 gd->ram_size = get_ram_size((void *)kw_sdram_bar(0), 325 kw_sdram_bs(0)); 326 return 0; 327 } 328 329 void dram_init_banksize(void) 330 { 331 int i; 332 333 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 334 gd->bd->bi_dram[i].start = kw_sdram_bar(i); 335 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), 336 kw_sdram_bs(i)); 337 } 338 } 339 340 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) 341 342 #define PHY_LED_SEL 0x18 343 #define PHY_LED0_LINK (0x5) 344 #define PHY_LED1_ACT (0x8<<4) 345 #define PHY_LED2_INT (0xe<<8) 346 #define PHY_SPEC_CTRL 0x1c 347 #define PHY_RGMII_CLK_STABLE (0x1<<10) 348 #define PHY_CLSA (0x1<<1) 349 350 /* Configure and enable MV88E3018 PHY */ 351 void reset_phy(void) 352 { 353 char *name = "egiga0"; 354 unsigned short reg; 355 356 if (miiphy_set_current_dev(name)) 357 return; 358 359 /* RGMII clk transition on data stable */ 360 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) 361 printf("Error reading PHY spec ctrl reg\n"); 362 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, 363 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) 364 printf("Error writing PHY spec ctrl reg\n"); 365 366 /* leds setup */ 367 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, 368 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) 369 printf("Error writing PHY LED reg\n"); 370 371 /* reset the phy */ 372 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 373 } 374 #else 375 /* Configure and enable MV88E1118 PHY on the piggy*/ 376 void reset_phy(void) 377 { 378 char *name = "egiga0"; 379 380 if (miiphy_set_current_dev(name)) 381 return; 382 383 /* reset the phy */ 384 miiphy_reset(name, CONFIG_PHY_BASE_ADR); 385 } 386 #endif 387 388 389 #if defined(CONFIG_HUSH_INIT_VAR) 390 int hush_init_var(void) 391 { 392 ivm_read_eeprom(); 393 return 0; 394 } 395 #endif 396 397 #if defined(CONFIG_BOOTCOUNT_LIMIT) 398 void bootcount_store(ulong a) 399 { 400 volatile ulong *save_addr; 401 volatile ulong size = 0; 402 int i; 403 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 404 size += gd->bd->bi_dram[i].size; 405 } 406 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 407 writel(a, save_addr); 408 writel(BOOTCOUNT_MAGIC, &save_addr[1]); 409 } 410 411 ulong bootcount_load(void) 412 { 413 volatile ulong *save_addr; 414 volatile ulong size = 0; 415 int i; 416 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 417 size += gd->bd->bi_dram[i].size; 418 } 419 save_addr = (ulong*)(size - BOOTCOUNT_ADDR); 420 if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC) 421 return 0; 422 else 423 return readl(save_addr); 424 } 425 #endif 426 427 #if defined(CONFIG_SOFT_I2C) 428 void set_sda(int state) 429 { 430 I2C_ACTIVE; 431 I2C_SDA(state); 432 } 433 434 void set_scl(int state) 435 { 436 I2C_SCL(state); 437 } 438 439 int get_sda(void) 440 { 441 I2C_TRISTATE; 442 return I2C_READ; 443 } 444 445 int get_scl(void) 446 { 447 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; 448 } 449 #endif 450 451 #if defined(CONFIG_SYS_EEPROM_WREN) 452 int eeprom_write_enable(unsigned dev_addr, int state) 453 { 454 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); 455 456 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); 457 } 458 #endif 459