1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2008 - 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 */ 19 20 #include <common.h> 21 #include <ioports.h> 22 #include <mpc83xx.h> 23 #include <i2c.h> 24 #include <miiphy.h> 25 #include <asm/io.h> 26 #include <asm/mmu.h> 27 #include <asm/processor.h> 28 #include <pci.h> 29 #include <libfdt.h> 30 #include <post.h> 31 32 #include "../common/common.h" 33 34 const qe_iop_conf_t qe_iop_conf_tab[] = { 35 /* port pin dir open_drain assign */ 36 #if defined(CONFIG_MPC8360) 37 /* MDIO */ 38 {0, 1, 3, 0, 2}, /* MDIO */ 39 {0, 2, 1, 0, 1}, /* MDC */ 40 41 /* UCC4 - UEC */ 42 {1, 14, 1, 0, 1}, /* TxD0 */ 43 {1, 15, 1, 0, 1}, /* TxD1 */ 44 {1, 20, 2, 0, 1}, /* RxD0 */ 45 {1, 21, 2, 0, 1}, /* RxD1 */ 46 {1, 18, 1, 0, 1}, /* TX_EN */ 47 {1, 26, 2, 0, 1}, /* RX_DV */ 48 {1, 27, 2, 0, 1}, /* RX_ER */ 49 {1, 24, 2, 0, 1}, /* COL */ 50 {1, 25, 2, 0, 1}, /* CRS */ 51 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ 52 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ 53 54 /* DUART - UART2 */ 55 {5, 0, 1, 0, 2}, /* UART2_SOUT */ 56 {5, 2, 1, 0, 1}, /* UART2_RTS */ 57 {5, 3, 2, 0, 2}, /* UART2_SIN */ 58 {5, 1, 2, 0, 3}, /* UART2_CTS */ 59 #else 60 /* Local Bus */ 61 {0, 16, 1, 0, 3}, /* LA00 */ 62 {0, 17, 1, 0, 3}, /* LA01 */ 63 {0, 18, 1, 0, 3}, /* LA02 */ 64 {0, 19, 1, 0, 3}, /* LA03 */ 65 {0, 20, 1, 0, 3}, /* LA04 */ 66 {0, 21, 1, 0, 3}, /* LA05 */ 67 {0, 22, 1, 0, 3}, /* LA06 */ 68 {0, 23, 1, 0, 3}, /* LA07 */ 69 {0, 24, 1, 0, 3}, /* LA08 */ 70 {0, 25, 1, 0, 3}, /* LA09 */ 71 {0, 26, 1, 0, 3}, /* LA10 */ 72 {0, 27, 1, 0, 3}, /* LA11 */ 73 {0, 28, 1, 0, 3}, /* LA12 */ 74 {0, 29, 1, 0, 3}, /* LA13 */ 75 {0, 30, 1, 0, 3}, /* LA14 */ 76 {0, 31, 1, 0, 3}, /* LA15 */ 77 78 /* MDIO */ 79 {3, 4, 3, 0, 2}, /* MDIO */ 80 {3, 5, 1, 0, 2}, /* MDC */ 81 82 /* UCC4 - UEC */ 83 {1, 18, 1, 0, 1}, /* TxD0 */ 84 {1, 19, 1, 0, 1}, /* TxD1 */ 85 {1, 22, 2, 0, 1}, /* RxD0 */ 86 {1, 23, 2, 0, 1}, /* RxD1 */ 87 {1, 26, 2, 0, 1}, /* RxER */ 88 {1, 28, 2, 0, 1}, /* Rx_DV */ 89 {1, 30, 1, 0, 1}, /* TxEN */ 90 {1, 31, 2, 0, 1}, /* CRS */ 91 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ 92 #endif 93 94 /* END of table */ 95 {0, 0, 0, 0, QE_IOP_TAB_END}, 96 }; 97 98 static int board_init_i2c_busses(void) 99 { 100 I2C_MUX_DEVICE *dev = NULL; 101 uchar *buf; 102 103 /* Set up the Bus for the DTTs */ 104 buf = (unsigned char *) getenv("dtt_bus"); 105 if (buf != NULL) 106 dev = i2c_mux_ident_muxstring(buf); 107 if (dev == NULL) { 108 printf("Error couldn't add Bus for DTT\n"); 109 printf("please setup dtt_bus to where your\n"); 110 printf("DTT is found.\n"); 111 } 112 return 0; 113 } 114 115 #if defined(CONFIG_SUVD3) 116 const uint upma_table[] = { 117 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ 118 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ 119 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ 120 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ 121 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ 122 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ 123 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ 124 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ 125 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ 126 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ 127 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ 128 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ 129 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ 130 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ 131 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ 132 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ 133 }; 134 #endif 135 136 int board_early_init_r(void) 137 { 138 struct km_bec_fpga *base = 139 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 140 #if defined(CONFIG_SUVD3) 141 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 142 fsl_lbc_t *lbc = &immap->im_lbc; 143 u32 *mxmr = &lbc->mamr; 144 #endif 145 146 #if defined(CONFIG_MPC8360) 147 unsigned short svid; 148 /* 149 * Because of errata in the UCCs, we have to write to the reserved 150 * registers to slow the clocks down. 151 */ 152 svid = SVR_REV(mfspr(SVR)); 153 switch (svid) { 154 case 0x0020: 155 /* 156 * MPC8360ECE.pdf QE_ENET10 table 4: 157 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) 158 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) 159 */ 160 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); 161 break; 162 case 0x0021: 163 /* 164 * MPC8360ECE.pdf QE_ENET10 table 4: 165 * IMMR + 0x14AC[24:27] = 1010 166 */ 167 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), 168 0x00000050, 0x000000a0); 169 break; 170 } 171 #endif 172 173 /* enable the PHY on the PIGGY */ 174 setbits_8(&base->pgy_eth, 0x01); 175 /* enable the Unit LED (green) */ 176 setbits_8(&base->oprth, WRL_BOOT); 177 /* enable Application Buffer */ 178 setbits_8(&base->oprtl, OPRTL_XBUFENA); 179 180 #if defined(CONFIG_SUVD3) 181 /* configure UPMA for APP1 */ 182 upmconfig(UPMA, (uint *) upma_table, 183 sizeof(upma_table) / sizeof(uint)); 184 out_be32(mxmr, CONFIG_SYS_MAMR); 185 #endif 186 return 0; 187 } 188 189 int misc_init_r(void) 190 { 191 /* add board specific i2c busses */ 192 board_init_i2c_busses(); 193 return 0; 194 } 195 196 int last_stage_init(void) 197 { 198 #if defined(CONFIG_KMCOGE5NE) 199 struct bfticu_iomap *base = 200 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; 201 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; 202 203 if (dip_switch != 0) { 204 /* start bootloader */ 205 puts("DIP: Enabled\n"); 206 setenv("actual_bank", "0"); 207 } 208 #endif 209 set_km_env(); 210 return 0; 211 } 212 213 int fixed_sdram(void) 214 { 215 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 216 u32 msize = 0; 217 u32 ddr_size; 218 u32 ddr_size_log2; 219 220 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); 221 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); 222 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 223 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 224 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 225 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 226 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 227 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 228 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 229 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 230 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 231 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 232 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); 233 udelay(200); 234 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 235 236 msize = CONFIG_SYS_DDR_SIZE << 20; 237 disable_addr_trans(); 238 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); 239 enable_addr_trans(); 240 msize /= (1024 * 1024); 241 if (CONFIG_SYS_DDR_SIZE != msize) { 242 for (ddr_size = msize << 20, ddr_size_log2 = 0; 243 (ddr_size > 1); 244 ddr_size = ddr_size >> 1, ddr_size_log2++) 245 if (ddr_size & 1) 246 return -1; 247 out_be32(&im->sysconf.ddrlaw[0].ar, 248 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); 249 out_be32(&im->ddr.csbnds[0].csbnds, 250 (((msize / 16) - 1) & 0xff)); 251 } 252 253 return msize; 254 } 255 256 phys_size_t initdram(int board_type) 257 { 258 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 259 u32 msize = 0; 260 261 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 262 return -1; 263 264 out_be32(&im->sysconf.ddrlaw[0].bar, 265 CONFIG_SYS_DDR_BASE & LAWBAR_BAR); 266 msize = fixed_sdram(); 267 268 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 269 /* 270 * Initialize DDR ECC byte 271 */ 272 ddr_enable_ecc(msize * 1024 * 1024); 273 #endif 274 275 /* return total bus SDRAM size(bytes) -- DDR */ 276 return msize * 1024 * 1024; 277 } 278 279 int checkboard(void) 280 { 281 puts("Board: Keymile " CONFIG_KM_BOARD_NAME); 282 283 if (ethernet_present()) 284 puts(" with PIGGY."); 285 puts("\n"); 286 return 0; 287 } 288 289 #if defined(CONFIG_OF_BOARD_SETUP) 290 void ft_board_setup(void *blob, bd_t *bd) 291 { 292 ft_cpu_setup(blob, bd); 293 } 294 #endif 295 296 #if defined(CONFIG_HUSH_INIT_VAR) 297 int hush_init_var(void) 298 { 299 ivm_read_eeprom(); 300 return 0; 301 } 302 #endif 303 304 #if defined(CONFIG_POST) 305 int post_hotkeys_pressed(void) 306 { 307 int testpin = 0; 308 struct km_bec_fpga *base = 309 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 310 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); 311 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; 312 debug("post_hotkeys_pressed: %d\n", !testpin); 313 return testpin; 314 } 315 316 ulong post_word_load(void) 317 { 318 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 319 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr)); 320 return in_le32(addr); 321 322 } 323 void post_word_store(ulong value) 324 { 325 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 326 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value); 327 out_le32(addr, value); 328 } 329 330 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 331 { 332 *vstart = CONFIG_SYS_MEMTEST_START; 333 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; 334 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); 335 336 return 0; 337 } 338 #endif 339