1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2008 - 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 */ 19 20 #include <common.h> 21 #include <ioports.h> 22 #include <mpc83xx.h> 23 #include <i2c.h> 24 #include <miiphy.h> 25 #include <asm/io.h> 26 #include <asm/mmu.h> 27 #include <asm/processor.h> 28 #include <pci.h> 29 #include <libfdt.h> 30 #include <post.h> 31 32 #include "../common/common.h" 33 34 static const qe_iop_conf_t qe_iop_conf_tab[] = { 35 /* port pin dir open_drain assign */ 36 #if defined(CONFIG_MPC8360) 37 /* MDIO */ 38 {0, 1, 3, 0, 2}, /* MDIO */ 39 {0, 2, 1, 0, 1}, /* MDC */ 40 41 /* UCC4 - UEC */ 42 {1, 14, 1, 0, 1}, /* TxD0 */ 43 {1, 15, 1, 0, 1}, /* TxD1 */ 44 {1, 20, 2, 0, 1}, /* RxD0 */ 45 {1, 21, 2, 0, 1}, /* RxD1 */ 46 {1, 18, 1, 0, 1}, /* TX_EN */ 47 {1, 26, 2, 0, 1}, /* RX_DV */ 48 {1, 27, 2, 0, 1}, /* RX_ER */ 49 {1, 24, 2, 0, 1}, /* COL */ 50 {1, 25, 2, 0, 1}, /* CRS */ 51 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ 52 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ 53 54 /* DUART - UART2 */ 55 {5, 0, 1, 0, 2}, /* UART2_SOUT */ 56 {5, 2, 1, 0, 1}, /* UART2_RTS */ 57 {5, 3, 2, 0, 2}, /* UART2_SIN */ 58 {5, 1, 2, 0, 3}, /* UART2_CTS */ 59 #elif !defined(CONFIG_MPC8309) 60 /* Local Bus */ 61 {0, 16, 1, 0, 3}, /* LA00 */ 62 {0, 17, 1, 0, 3}, /* LA01 */ 63 {0, 18, 1, 0, 3}, /* LA02 */ 64 {0, 19, 1, 0, 3}, /* LA03 */ 65 {0, 20, 1, 0, 3}, /* LA04 */ 66 {0, 21, 1, 0, 3}, /* LA05 */ 67 {0, 22, 1, 0, 3}, /* LA06 */ 68 {0, 23, 1, 0, 3}, /* LA07 */ 69 {0, 24, 1, 0, 3}, /* LA08 */ 70 {0, 25, 1, 0, 3}, /* LA09 */ 71 {0, 26, 1, 0, 3}, /* LA10 */ 72 {0, 27, 1, 0, 3}, /* LA11 */ 73 {0, 28, 1, 0, 3}, /* LA12 */ 74 {0, 29, 1, 0, 3}, /* LA13 */ 75 {0, 30, 1, 0, 3}, /* LA14 */ 76 {0, 31, 1, 0, 3}, /* LA15 */ 77 78 /* MDIO */ 79 {3, 4, 3, 0, 2}, /* MDIO */ 80 {3, 5, 1, 0, 2}, /* MDC */ 81 82 /* UCC4 - UEC */ 83 {1, 18, 1, 0, 1}, /* TxD0 */ 84 {1, 19, 1, 0, 1}, /* TxD1 */ 85 {1, 22, 2, 0, 1}, /* RxD0 */ 86 {1, 23, 2, 0, 1}, /* RxD1 */ 87 {1, 26, 2, 0, 1}, /* RxER */ 88 {1, 28, 2, 0, 1}, /* Rx_DV */ 89 {1, 30, 1, 0, 1}, /* TxEN */ 90 {1, 31, 2, 0, 1}, /* CRS */ 91 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ 92 #endif 93 94 /* END of table */ 95 {0, 0, 0, 0, QE_IOP_TAB_END}, 96 }; 97 98 static int board_init_i2c_busses(void) 99 { 100 I2C_MUX_DEVICE *dev = NULL; 101 uchar *dtt_bus = (uchar *)"pca9547:70:a"; 102 103 /* Set up the Bus for the DTTs */ 104 dev = i2c_mux_ident_muxstring(dtt_bus); 105 if (dev == NULL) 106 printf("Error couldn't add Bus for DTT\n"); 107 108 return 0; 109 } 110 111 #if defined(CONFIG_SUVD3) 112 const uint upma_table[] = { 113 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ 114 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ 115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ 116 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ 117 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ 118 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ 119 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ 120 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ 121 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ 122 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ 123 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ 124 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ 125 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ 126 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ 127 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ 128 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ 129 }; 130 #endif 131 132 static int piggy_present(void) 133 { 134 struct km_bec_fpga __iomem *base = 135 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; 136 137 return in_8(&base->bprth) & PIGGY_PRESENT; 138 } 139 140 #if defined(CONFIG_KMVECT1) 141 int ethernet_present(void) 142 { 143 /* ethernet port connected to simple switch without piggy */ 144 return 1; 145 } 146 #else 147 int ethernet_present(void) 148 { 149 return piggy_present(); 150 } 151 #endif 152 153 154 int board_early_init_r(void) 155 { 156 struct km_bec_fpga *base = 157 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 158 #if defined(CONFIG_SUVD3) 159 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 160 fsl_lbc_t *lbc = &immap->im_lbc; 161 u32 *mxmr = &lbc->mamr; 162 #endif 163 164 #if defined(CONFIG_MPC8360) 165 unsigned short svid; 166 /* 167 * Because of errata in the UCCs, we have to write to the reserved 168 * registers to slow the clocks down. 169 */ 170 svid = SVR_REV(mfspr(SVR)); 171 switch (svid) { 172 case 0x0020: 173 /* 174 * MPC8360ECE.pdf QE_ENET10 table 4: 175 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) 176 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) 177 */ 178 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); 179 break; 180 case 0x0021: 181 /* 182 * MPC8360ECE.pdf QE_ENET10 table 4: 183 * IMMR + 0x14AC[24:27] = 1010 184 */ 185 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), 186 0x00000050, 0x000000a0); 187 break; 188 } 189 #endif 190 191 /* enable the PHY on the PIGGY */ 192 setbits_8(&base->pgy_eth, 0x01); 193 /* enable the Unit LED (green) */ 194 setbits_8(&base->oprth, WRL_BOOT); 195 /* enable Application Buffer */ 196 setbits_8(&base->oprtl, OPRTL_XBUFENA); 197 198 #if defined(CONFIG_SUVD3) 199 /* configure UPMA for APP1 */ 200 upmconfig(UPMA, (uint *) upma_table, 201 sizeof(upma_table) / sizeof(uint)); 202 out_be32(mxmr, CONFIG_SYS_MAMR); 203 #endif 204 return 0; 205 } 206 207 int misc_init_r(void) 208 { 209 /* add board specific i2c busses */ 210 board_init_i2c_busses(); 211 return 0; 212 } 213 214 #if defined(CONFIG_KMVECT1) 215 #include <mv88e6352.h> 216 /* Marvell MV88E6122 switch configuration */ 217 static struct mv88e_sw_reg extsw_conf[] = { 218 /* port 1, FRONT_MDI, autoneg */ 219 { PORT(1), PORT_PHY, NO_SPEED_FOR }, 220 { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 221 { PHY(1), PHY_1000_CTRL, NO_ADV }, 222 { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 223 { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 224 FULL_DUPLEX }, 225 /* port 2, unused */ 226 { PORT(2), PORT_CTRL, PORT_DIS }, 227 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 228 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 229 /* port 3, BP_MII (CPU), PHY mode, 100BASE */ 230 { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 231 /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */ 232 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 233 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 234 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 235 /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */ 236 { PORT(5), PORT_STATUS, NO_PHY_DETECT }, 237 { PORT(5), PORT_PHY, SPEED_1000_FOR }, 238 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 239 /* 240 * Errata Fix: 1.9V Output from Internal 1.8V Regulator, 241 * acc . MV-S300889-00D.pdf , clause 4.5 242 */ 243 { PORT(5), 0x1A, 0xADB1 }, 244 /* port 6, unused, this port has no phy */ 245 { PORT(6), PORT_CTRL, PORT_DIS }, 246 /* 247 * Errata Fix: 1.9V Output from Internal 1.8V Regulator, 248 * acc . MV-S300889-00D.pdf , clause 4.5 249 */ 250 { PORT(5), 0x1A, 0xADB1 }, 251 }; 252 #endif 253 254 int last_stage_init(void) 255 { 256 #if defined(CONFIG_KMVECT1) 257 struct km_bec_fpga __iomem *base = 258 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; 259 u8 tmp_reg; 260 261 /* Release mv88e6122 from reset */ 262 tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */ 263 out_8(&base->res1[0], tmp_reg); /* GP28 as output */ 264 tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */ 265 out_8(&base->gprt3, tmp_reg); 266 267 /* configure MV88E6122 switch */ 268 char *name = "UEC2"; 269 270 if (miiphy_set_current_dev(name)) 271 return 0; 272 273 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 274 ARRAY_SIZE(extsw_conf)); 275 276 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 277 278 if (piggy_present()) { 279 setenv("ethact", "UEC2"); 280 setenv("netdev", "eth1"); 281 puts("using PIGGY for network boot\n"); 282 } else { 283 setenv("netdev", "eth0"); 284 puts("using frontport for network boot\n"); 285 } 286 #endif 287 288 #if defined(CONFIG_KMCOGE5NE) 289 struct bfticu_iomap *base = 290 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; 291 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; 292 293 if (dip_switch != 0) { 294 /* start bootloader */ 295 puts("DIP: Enabled\n"); 296 setenv("actual_bank", "0"); 297 } 298 #endif 299 set_km_env(); 300 return 0; 301 } 302 303 static int fixed_sdram(void) 304 { 305 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 306 u32 msize = 0; 307 u32 ddr_size; 308 u32 ddr_size_log2; 309 310 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); 311 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); 312 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 313 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 314 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 315 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 316 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 317 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 318 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 319 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 320 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 321 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 322 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); 323 udelay(200); 324 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 325 326 msize = CONFIG_SYS_DDR_SIZE << 20; 327 disable_addr_trans(); 328 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); 329 enable_addr_trans(); 330 msize /= (1024 * 1024); 331 if (CONFIG_SYS_DDR_SIZE != msize) { 332 for (ddr_size = msize << 20, ddr_size_log2 = 0; 333 (ddr_size > 1); 334 ddr_size = ddr_size >> 1, ddr_size_log2++) 335 if (ddr_size & 1) 336 return -1; 337 out_be32(&im->sysconf.ddrlaw[0].ar, 338 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); 339 out_be32(&im->ddr.csbnds[0].csbnds, 340 (((msize / 16) - 1) & 0xff)); 341 } 342 343 return msize; 344 } 345 346 phys_size_t initdram(int board_type) 347 { 348 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 349 u32 msize = 0; 350 351 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 352 return -1; 353 354 out_be32(&im->sysconf.ddrlaw[0].bar, 355 CONFIG_SYS_DDR_BASE & LAWBAR_BAR); 356 msize = fixed_sdram(); 357 358 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 359 /* 360 * Initialize DDR ECC byte 361 */ 362 ddr_enable_ecc(msize * 1024 * 1024); 363 #endif 364 365 /* return total bus SDRAM size(bytes) -- DDR */ 366 return msize * 1024 * 1024; 367 } 368 369 int checkboard(void) 370 { 371 puts("Board: Keymile " CONFIG_KM_BOARD_NAME); 372 373 if (piggy_present()) 374 puts(" with PIGGY."); 375 puts("\n"); 376 return 0; 377 } 378 379 #if defined(CONFIG_OF_BOARD_SETUP) 380 void ft_board_setup(void *blob, bd_t *bd) 381 { 382 ft_cpu_setup(blob, bd); 383 } 384 #endif 385 386 #if defined(CONFIG_HUSH_INIT_VAR) 387 int hush_init_var(void) 388 { 389 ivm_read_eeprom(); 390 return 0; 391 } 392 #endif 393 394 #if defined(CONFIG_POST) 395 int post_hotkeys_pressed(void) 396 { 397 int testpin = 0; 398 struct km_bec_fpga *base = 399 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 400 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); 401 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; 402 debug("post_hotkeys_pressed: %d\n", !testpin); 403 return testpin; 404 } 405 406 ulong post_word_load(void) 407 { 408 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 409 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr)); 410 return in_le32(addr); 411 412 } 413 void post_word_store(ulong value) 414 { 415 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 416 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value); 417 out_le32(addr, value); 418 } 419 420 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 421 { 422 *vstart = CONFIG_SYS_MEMTEST_START; 423 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; 424 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); 425 426 return 0; 427 } 428 #endif 429