1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2008 - 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 */ 19 20 #include <common.h> 21 #include <ioports.h> 22 #include <mpc83xx.h> 23 #include <i2c.h> 24 #include <miiphy.h> 25 #include <asm/io.h> 26 #include <asm/mmu.h> 27 #include <asm/processor.h> 28 #include <pci.h> 29 #include <libfdt.h> 30 31 #include "../common/common.h" 32 33 const qe_iop_conf_t qe_iop_conf_tab[] = { 34 /* port pin dir open_drain assign */ 35 #if defined(CONFIG_KMETER1) 36 /* MDIO */ 37 {0, 1, 3, 0, 2}, /* MDIO */ 38 {0, 2, 1, 0, 1}, /* MDC */ 39 40 /* UCC4 - UEC */ 41 {1, 14, 1, 0, 1}, /* TxD0 */ 42 {1, 15, 1, 0, 1}, /* TxD1 */ 43 {1, 20, 2, 0, 1}, /* RxD0 */ 44 {1, 21, 2, 0, 1}, /* RxD1 */ 45 {1, 18, 1, 0, 1}, /* TX_EN */ 46 {1, 26, 2, 0, 1}, /* RX_DV */ 47 {1, 27, 2, 0, 1}, /* RX_ER */ 48 {1, 24, 2, 0, 1}, /* COL */ 49 {1, 25, 2, 0, 1}, /* CRS */ 50 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ 51 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ 52 53 /* DUART - UART2 */ 54 {5, 0, 1, 0, 2}, /* UART2_SOUT */ 55 {5, 2, 1, 0, 1}, /* UART2_RTS */ 56 {5, 3, 2, 0, 2}, /* UART2_SIN */ 57 {5, 1, 2, 0, 3}, /* UART2_CTS */ 58 #else 59 /* Local Bus */ 60 {0, 16, 1, 0, 3}, /* LA00 */ 61 {0, 17, 1, 0, 3}, /* LA01 */ 62 {0, 18, 1, 0, 3}, /* LA02 */ 63 {0, 19, 1, 0, 3}, /* LA03 */ 64 {0, 20, 1, 0, 3}, /* LA04 */ 65 {0, 21, 1, 0, 3}, /* LA05 */ 66 {0, 22, 1, 0, 3}, /* LA06 */ 67 {0, 23, 1, 0, 3}, /* LA07 */ 68 {0, 24, 1, 0, 3}, /* LA08 */ 69 {0, 25, 1, 0, 3}, /* LA09 */ 70 {0, 26, 1, 0, 3}, /* LA10 */ 71 {0, 27, 1, 0, 3}, /* LA11 */ 72 {0, 28, 1, 0, 3}, /* LA12 */ 73 {0, 29, 1, 0, 3}, /* LA13 */ 74 {0, 30, 1, 0, 3}, /* LA14 */ 75 {0, 31, 1, 0, 3}, /* LA15 */ 76 77 /* MDIO */ 78 {3, 4, 3, 0, 2}, /* MDIO */ 79 {3, 5, 1, 0, 2}, /* MDC */ 80 81 /* UCC4 - UEC */ 82 {1, 18, 1, 0, 1}, /* TxD0 */ 83 {1, 19, 1, 0, 1}, /* TxD1 */ 84 {1, 22, 2, 0, 1}, /* RxD0 */ 85 {1, 23, 2, 0, 1}, /* RxD1 */ 86 {1, 26, 2, 0, 1}, /* RxER */ 87 {1, 28, 2, 0, 1}, /* Rx_DV */ 88 {1, 30, 1, 0, 1}, /* TxEN */ 89 {1, 31, 2, 0, 1}, /* CRS */ 90 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ 91 #endif 92 93 /* END of table */ 94 {0, 0, 0, 0, QE_IOP_TAB_END}, 95 }; 96 97 static int board_init_i2c_busses(void) 98 { 99 I2C_MUX_DEVICE *dev = NULL; 100 uchar *buf; 101 102 /* Set up the Bus for the DTTs */ 103 buf = (unsigned char *) getenv("dtt_bus"); 104 if (buf != NULL) 105 dev = i2c_mux_ident_muxstring(buf); 106 if (dev == NULL) { 107 printf("Error couldn't add Bus for DTT\n"); 108 printf("please setup dtt_bus to where your\n"); 109 printf("DTT is found.\n"); 110 } 111 return 0; 112 } 113 114 #if defined(CONFIG_SUVD3) 115 const uint upma_table[] = { 116 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ 117 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ 118 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ 119 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ 120 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ 121 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ 122 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ 123 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ 124 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ 125 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ 126 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ 127 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ 128 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ 129 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ 130 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ 131 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ 132 }; 133 #endif 134 135 int board_early_init_r(void) 136 { 137 struct km_bec_fpga *base = 138 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 139 #if defined(CONFIG_SUVD3) 140 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 141 fsl_lbc_t *lbc = &immap->im_lbc; 142 u32 *mxmr = &lbc->mamr; 143 #endif 144 145 #if defined(CONFIG_MPC8360) 146 unsigned short svid; 147 /* 148 * Because of errata in the UCCs, we have to write to the reserved 149 * registers to slow the clocks down. 150 */ 151 svid = SVR_REV(mfspr(SVR)); 152 switch (svid) { 153 case 0x0020: 154 /* 155 * MPC8360ECE.pdf QE_ENET10 table 4: 156 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) 157 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) 158 */ 159 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); 160 break; 161 case 0x0021: 162 /* 163 * MPC8360ECE.pdf QE_ENET10 table 4: 164 * IMMR + 0x14AC[24:27] = 1010 165 */ 166 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), 167 0x00000050, 0x000000a0); 168 break; 169 } 170 #endif 171 172 /* enable the PHY on the PIGGY */ 173 setbits_8(&base->pgy_eth, 0x01); 174 /* enable the Unit LED (green) */ 175 setbits_8(&base->oprth, WRL_BOOT); 176 177 #if defined(CONFIG_SUVD3) 178 /* configure UPMA for APP1 */ 179 upmconfig(UPMA, (uint *) upma_table, 180 sizeof(upma_table) / sizeof(uint)); 181 out_be32(mxmr, CONFIG_SYS_MAMR); 182 #endif 183 return 0; 184 } 185 186 int misc_init_r(void) 187 { 188 /* add board specific i2c busses */ 189 board_init_i2c_busses(); 190 return 0; 191 } 192 193 int last_stage_init(void) 194 { 195 set_km_env(); 196 return 0; 197 } 198 199 int fixed_sdram(void) 200 { 201 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 202 u32 msize = 0; 203 u32 ddr_size; 204 u32 ddr_size_log2; 205 206 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); 207 out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS); 208 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 209 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 210 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 211 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 212 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 213 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 214 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 215 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 216 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 217 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 218 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); 219 udelay(200); 220 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 221 222 msize = CONFIG_SYS_DDR_SIZE << 20; 223 disable_addr_trans(); 224 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); 225 enable_addr_trans(); 226 msize /= (1024 * 1024); 227 if (CONFIG_SYS_DDR_SIZE != msize) { 228 for (ddr_size = msize << 20, ddr_size_log2 = 0; 229 (ddr_size > 1); 230 ddr_size = ddr_size >> 1, ddr_size_log2++) 231 if (ddr_size & 1) 232 return -1; 233 out_be32(&im->sysconf.ddrlaw[0].ar, 234 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); 235 out_be32(&im->ddr.csbnds[0].csbnds, 236 (((msize / 16) - 1) & 0xff)); 237 } 238 239 return msize; 240 } 241 242 phys_size_t initdram(int board_type) 243 { 244 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 245 u32 msize = 0; 246 247 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 248 return -1; 249 250 out_be32(&im->sysconf.ddrlaw[0].bar, 251 CONFIG_SYS_DDR_BASE & LAWBAR_BAR); 252 msize = fixed_sdram(); 253 254 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 255 /* 256 * Initialize DDR ECC byte 257 */ 258 ddr_enable_ecc(msize * 1024 * 1024); 259 #endif 260 261 /* return total bus SDRAM size(bytes) -- DDR */ 262 return msize * 1024 * 1024; 263 } 264 265 int checkboard(void) 266 { 267 puts("Board: Keymile " CONFIG_KM_BOARD_NAME); 268 269 if (ethernet_present()) 270 puts(" with PIGGY."); 271 puts("\n"); 272 return 0; 273 } 274 275 #if defined(CONFIG_OF_BOARD_SETUP) 276 void ft_board_setup(void *blob, bd_t *bd) 277 { 278 ft_cpu_setup(blob, bd); 279 } 280 #endif 281 282 #if defined(CONFIG_HUSH_INIT_VAR) 283 int hush_init_var(void) 284 { 285 ivm_read_eeprom(); 286 return 0; 287 } 288 #endif 289