1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2210c8c00SHeiko Schocher /* 3210c8c00SHeiko Schocher * (C) Copyright 2008 4210c8c00SHeiko Schocher * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5210c8c00SHeiko Schocher */ 6210c8c00SHeiko Schocher 7210c8c00SHeiko Schocher #ifndef __KEYMILE_COMMON_H 8210c8c00SHeiko Schocher #define __KEYMILE_COMMON_H 9210c8c00SHeiko Schocher 10b11f53f3SHeiko Schocher #define WRG_RESET 0x80 11b11f53f3SHeiko Schocher #define H_OPORTS_14 0x40 12b11f53f3SHeiko Schocher #define WRG_LED 0x02 13b11f53f3SHeiko Schocher #define WRL_BOOT 0x01 14b11f53f3SHeiko Schocher 155758dd76SStefan Bigler #define OPRTL_XBUFENA 0x20 165758dd76SStefan Bigler 17b11f53f3SHeiko Schocher #define H_OPORTS_SCC4_ENA 0x10 18b11f53f3SHeiko Schocher #define H_OPORTS_SCC4_FD_ENA 0x04 19b11f53f3SHeiko Schocher #define H_OPORTS_FCC1_PW_DWN 0x01 20b11f53f3SHeiko Schocher 21b11f53f3SHeiko Schocher #define PIGGY_PRESENT 0x80 22b11f53f3SHeiko Schocher 23b11f53f3SHeiko Schocher struct km_bec_fpga { 24b11f53f3SHeiko Schocher unsigned char id; 25b11f53f3SHeiko Schocher unsigned char rev; 26b11f53f3SHeiko Schocher unsigned char oprth; 27b11f53f3SHeiko Schocher unsigned char oprtl; 28b11f53f3SHeiko Schocher unsigned char res1[3]; 29b11f53f3SHeiko Schocher unsigned char bprth; 30b11f53f3SHeiko Schocher unsigned char bprtl; 3195209b66SThomas Herzmann unsigned char gprt3; 3295209b66SThomas Herzmann unsigned char gprt2; 3395209b66SThomas Herzmann unsigned char gprt1; 3495209b66SThomas Herzmann unsigned char gprt0; 3595209b66SThomas Herzmann unsigned char res2[2]; 36b11f53f3SHeiko Schocher unsigned char prst; 37b11f53f3SHeiko Schocher unsigned char res3[0xfff0]; 38b11f53f3SHeiko Schocher unsigned char pgy_id; 39b11f53f3SHeiko Schocher unsigned char pgy_rev; 40b11f53f3SHeiko Schocher unsigned char pgy_outputs; 41b11f53f3SHeiko Schocher unsigned char pgy_eth; 42b11f53f3SHeiko Schocher }; 43b11f53f3SHeiko Schocher 44f30c62bbSHuber, Andreas #define BFTICU_DIPSWITCH_MASK 0x0f 45f30c62bbSHuber, Andreas 46f30c62bbSHuber, Andreas /* 47f30c62bbSHuber, Andreas * BFTICU FPGA iomap 48f30c62bbSHuber, Andreas * BFTICU is used on mgcoge and mgocge3ne 49f30c62bbSHuber, Andreas */ 50f30c62bbSHuber, Andreas struct bfticu_iomap { 51f30c62bbSHuber, Andreas u8 xi_ena; /* General defect enable */ 52f30c62bbSHuber, Andreas u8 pack1[3]; 53f30c62bbSHuber, Andreas u8 en_csn; 54f30c62bbSHuber, Andreas u8 pack2; 55f30c62bbSHuber, Andreas u8 safe_mem; 56f30c62bbSHuber, Andreas u8 pack3; 57f30c62bbSHuber, Andreas u8 id; 58f30c62bbSHuber, Andreas u8 pack4; 59f30c62bbSHuber, Andreas u8 rev; 60f30c62bbSHuber, Andreas u8 build; 61f30c62bbSHuber, Andreas u8 p_frc; 62f30c62bbSHuber, Andreas u8 p_msk; 63f30c62bbSHuber, Andreas u8 pack5[2]; 64f30c62bbSHuber, Andreas u8 xg_int; 65f30c62bbSHuber, Andreas u8 pack6[15]; 66f30c62bbSHuber, Andreas u8 s_conf; 67f30c62bbSHuber, Andreas u8 pack7; 68f30c62bbSHuber, Andreas u8 dmx_conf12; 69f30c62bbSHuber, Andreas u8 pack8; 70f30c62bbSHuber, Andreas u8 s_clkslv; 71f30c62bbSHuber, Andreas u8 pack9[11]; 72f30c62bbSHuber, Andreas u8 d_conf; 73f30c62bbSHuber, Andreas u8 d_mask_ca; 74f30c62bbSHuber, Andreas u8 d_pll_del; 75f30c62bbSHuber, Andreas u8 pack10[16]; 76f30c62bbSHuber, Andreas u8 t_conf_ca; 77f30c62bbSHuber, Andreas u8 t_mask_ca; 78f30c62bbSHuber, Andreas u8 pack11[13]; 79f30c62bbSHuber, Andreas u8 m_def0; 80f30c62bbSHuber, Andreas u8 m_def1; 81f30c62bbSHuber, Andreas u8 m_def2; 82f30c62bbSHuber, Andreas u8 m_def3; 83f30c62bbSHuber, Andreas u8 m_def4; 84f30c62bbSHuber, Andreas u8 m_def5; 85f30c62bbSHuber, Andreas u8 m_def_trap0; 86f30c62bbSHuber, Andreas u8 m_def_trap1; 87f30c62bbSHuber, Andreas u8 m_def_trap2; 88f30c62bbSHuber, Andreas u8 m_def_trap3; 89f30c62bbSHuber, Andreas u8 m_def_trap4; 90f30c62bbSHuber, Andreas u8 m_def_trap5; 91f30c62bbSHuber, Andreas u8 m_mask_def0; 92f30c62bbSHuber, Andreas u8 m_mask_def1; 93f30c62bbSHuber, Andreas u8 m_mask_def2; 94f30c62bbSHuber, Andreas u8 m_mask_def3; 95f30c62bbSHuber, Andreas u8 m_mask_def4; 96f30c62bbSHuber, Andreas u8 m_mask_def5; 97f30c62bbSHuber, Andreas u8 m_def_mask0; 98f30c62bbSHuber, Andreas u8 m_def_mask1; 99f30c62bbSHuber, Andreas u8 m_def_mask2; 100f30c62bbSHuber, Andreas u8 m_def_mask3; 101f30c62bbSHuber, Andreas u8 m_def_mask4; 102f30c62bbSHuber, Andreas u8 m_def_mask5; 103f30c62bbSHuber, Andreas u8 m_def_pri; 104f30c62bbSHuber, Andreas u8 pack12[11]; 105f30c62bbSHuber, Andreas u8 hw_status; 106f30c62bbSHuber, Andreas u8 pack13; 107f30c62bbSHuber, Andreas u8 hw_control1; 108f30c62bbSHuber, Andreas u8 hw_control2; 109f30c62bbSHuber, Andreas u8 hw_control3; 110f30c62bbSHuber, Andreas u8 pack14[7]; 111f30c62bbSHuber, Andreas u8 led_on; /* Leds */ 112f30c62bbSHuber, Andreas u8 pack15; 113f30c62bbSHuber, Andreas u8 sfp_control; /* SFP modules */ 114f30c62bbSHuber, Andreas u8 pack16; 115f30c62bbSHuber, Andreas u8 alarm_control; /* Alarm output */ 116f30c62bbSHuber, Andreas u8 pack17; 117f30c62bbSHuber, Andreas u8 icps; /* ICN clock pulse shaping */ 118f30c62bbSHuber, Andreas u8 mswitch; /* Read mode switch */ 119f30c62bbSHuber, Andreas u8 pack18[6]; 120f30c62bbSHuber, Andreas u8 pb_dbug; 121f30c62bbSHuber, Andreas }; 122f30c62bbSHuber, Andreas 1230d015202SHeiko Schocher #if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET) 1240d015202SHeiko Schocher #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0 1250d015202SHeiko Schocher #endif 1260d015202SHeiko Schocher 127210c8c00SHeiko Schocher int ethernet_present(void); 12860c4ae00SValentin Longchamp int ivm_read_eeprom(unsigned char *buf, int len); 12916ac90c7SValentin Longchamp int ivm_analyze_eeprom(unsigned char *buf, int len); 130210c8c00SHeiko Schocher 131b37f7724SValentin Longchamp int trigger_fpga_config(void); 132b37f7724SValentin Longchamp int wait_for_fpga_config(void); 133b37f7724SValentin Longchamp int fpga_reset(void); 134b37f7724SValentin Longchamp int toggle_eeprom_spi_bus(void); 135b37f7724SValentin Longchamp 136d3f1d6f4SHolger Brunck int get_testpin(void); 137d3f1d6f4SHolger Brunck 138f1fef1d8SHeiko Schocher int set_km_env(void); 139b11f53f3SHeiko Schocher 140e792affeSHolger Brunck #define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ 141e792affeSHolger Brunck #define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) 142e792affeSHolger Brunck 143b11f53f3SHeiko Schocher int i2c_soft_read_pin(void); 1444f745bf4SHolger Brunck int i2c_make_abort(void); 145210c8c00SHeiko Schocher #endif /* __KEYMILE_COMMON_H */ 146