1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * K+P iMX6Q KP_IMX6Q_TPC board configuration 4 * 5 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> 6 */ 7 8 #include <common.h> 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/iomux-v3.h> 19 #include <asm/mach-imx/mxc_i2c.h> 20 #include <asm/io.h> 21 #include <errno.h> 22 #include <fuse.h> 23 #include <fsl_esdhc.h> 24 #include <i2c.h> 25 #include <mmc.h> 26 #include <spl.h> 27 28 #define UART_PAD_CTRL \ 29 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 30 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 31 32 #define USDHC_PAD_CTRL \ 33 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 34 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static void ccgr_init(void) 39 { 40 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 41 42 writel(0x00C03F3F, &ccm->CCGR0); 43 writel(0x0030FC03, &ccm->CCGR1); 44 writel(0x0FFFC000, &ccm->CCGR2); 45 writel(0x3FF00000, &ccm->CCGR3); 46 writel(0x00FFF300, &ccm->CCGR4); 47 writel(0x0F0000C3, &ccm->CCGR5); 48 writel(0x000003FF, &ccm->CCGR6); 49 } 50 51 /* onboard microSD */ 52 static iomux_v3_cfg_t const usdhc2_pads[] = { 53 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 54 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 55 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 56 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 57 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 58 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 59 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 60 }; 61 62 /* eMMC */ 63 static iomux_v3_cfg_t const usdhc4_pads[] = { 64 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 65 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 66 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 67 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 68 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 69 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 70 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 71 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 72 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 73 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 74 }; 75 76 /* SD */ 77 static void setup_iomux_sd(void) 78 { 79 SETUP_IOMUX_PADS(usdhc2_pads); 80 SETUP_IOMUX_PADS(usdhc4_pads); 81 } 82 83 /* UART */ 84 static iomux_v3_cfg_t const uart1_pads[] = { 85 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 86 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 87 }; 88 89 static void setup_iomux_uart(void) 90 { 91 SETUP_IOMUX_PADS(uart1_pads); 92 } 93 94 /* USB */ 95 static iomux_v3_cfg_t const usb_pads[] = { 96 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), 97 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 98 }; 99 100 static void setup_iomux_usb(void) 101 { 102 SETUP_IOMUX_PADS(usb_pads); 103 } 104 105 /* DDR3 */ 106 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 107 .dram_sdclk_0 = 0x00000030, 108 .dram_sdclk_1 = 0x00000030, 109 .dram_cas = 0x00000030, 110 .dram_ras = 0x00000030, 111 .dram_reset = 0x00000030, 112 .dram_sdcke0 = 0x00003000, 113 .dram_sdcke1 = 0x00003000, 114 .dram_sdba2 = 0x00000000, 115 .dram_sdodt0 = 0x00000030, 116 .dram_sdodt1 = 0x00000030, 117 118 .dram_sdqs0 = 0x00000018, 119 .dram_sdqs1 = 0x00000018, 120 .dram_sdqs2 = 0x00000018, 121 .dram_sdqs3 = 0x00000018, 122 .dram_sdqs4 = 0x00000018, 123 .dram_sdqs5 = 0x00000018, 124 .dram_sdqs6 = 0x00000018, 125 .dram_sdqs7 = 0x00000018, 126 127 .dram_dqm0 = 0x00000018, 128 .dram_dqm1 = 0x00000018, 129 .dram_dqm2 = 0x00000018, 130 .dram_dqm3 = 0x00000018, 131 .dram_dqm4 = 0x00000018, 132 .dram_dqm5 = 0x00000018, 133 .dram_dqm6 = 0x00000018, 134 .dram_dqm7 = 0x00000018, 135 }; 136 137 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 138 .grp_ddr_type = 0x000c0000, 139 .grp_ddrmode_ctl = 0x00020000, 140 .grp_ddrpke = 0x00000000, 141 .grp_addds = 0x00000030, 142 .grp_ctlds = 0x00000030, 143 .grp_ddrmode = 0x00020000, 144 .grp_b0ds = 0x00000018, 145 .grp_b1ds = 0x00000018, 146 .grp_b2ds = 0x00000018, 147 .grp_b3ds = 0x00000018, 148 .grp_b4ds = 0x00000018, 149 .grp_b5ds = 0x00000018, 150 .grp_b6ds = 0x00000018, 151 .grp_b7ds = 0x00000018, 152 }; 153 154 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { 155 .p0_mpwldectrl0 = 0x001F001F, 156 .p0_mpwldectrl1 = 0x001F001F, 157 .p1_mpwldectrl0 = 0x001F001F, 158 .p1_mpwldectrl1 = 0x001F001F, 159 .p0_mpdgctrl0 = 0x43270338, 160 .p0_mpdgctrl1 = 0x03200314, 161 .p1_mpdgctrl0 = 0x431A032F, 162 .p1_mpdgctrl1 = 0x03200263, 163 .p0_mprddlctl = 0x4B434748, 164 .p1_mprddlctl = 0x4445404C, 165 .p0_mpwrdlctl = 0x38444542, 166 .p1_mpwrdlctl = 0x4935493A, 167 }; 168 169 /* MT41K256M16 (4Gb density) */ 170 static const struct mx6_ddr3_cfg mt41k256m16 = { 171 .mem_speed = 1600, 172 .density = 4, 173 .width = 16, 174 .banks = 8, 175 .rowaddr = 15, 176 .coladdr = 10, 177 .pagesz = 2, 178 .trcd = 1375, 179 .trcmin = 4875, 180 .trasmin = 3500, 181 }; 182 183 #ifdef CONFIG_MX6_DDRCAL 184 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) 185 { 186 struct mx6_mmdc_calibration calibration = {0}; 187 188 mmdc_read_calibration(sysinfo, &calibration); 189 190 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); 191 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); 192 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); 193 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); 194 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); 195 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); 196 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); 197 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); 198 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); 199 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); 200 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); 201 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); 202 } 203 204 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) 205 { 206 int ret; 207 208 /* Perform DDR DRAM calibration */ 209 udelay(100); 210 ret = mmdc_do_write_level_calibration(sysinfo); 211 if (ret) { 212 printf("DDR: Write level calibration error [%d]\n", ret); 213 return; 214 } 215 216 ret = mmdc_do_dqs_calibration(sysinfo); 217 if (ret) { 218 printf("DDR: DQS calibration error [%d]\n", ret); 219 return; 220 } 221 222 spl_dram_print_cal(sysinfo); 223 } 224 #endif /* CONFIG_MX6_DDRCAL */ 225 226 static void spl_dram_init(void) 227 { 228 struct mx6_ddr_sysinfo sysinfo = { 229 /* width of data bus:0=16,1=32,2=64 */ 230 .dsize = 2, 231 /* config for full 4GB range so that get_mem_size() works */ 232 .cs_density = 32, /* 32Gb per CS */ 233 /* single chip select */ 234 .ncs = 1, 235 .cs1_mirror = 0, 236 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 237 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 238 .walat = 1, /* Write additional latency */ 239 .ralat = 5, /* Read additional latency */ 240 .mif3_mode = 3, /* Command prediction working mode */ 241 .bi_on = 1, /* Bank interleaving enabled */ 242 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 243 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 244 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 245 .ddr_type = DDR_TYPE_DDR3, 246 .refsel = 1, /* Refresh cycles at 32KHz */ 247 .refr = 7, /* 8 refresh commands per refresh cycle */ 248 }; 249 250 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 251 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16); 252 253 #ifdef CONFIG_MX6_DDRCAL 254 spl_dram_perform_cal(&sysinfo); 255 #endif 256 } 257 258 struct fsl_esdhc_cfg usdhc_cfg[] = { 259 {USDHC2_BASE_ADDR}, 260 {USDHC4_BASE_ADDR}, 261 }; 262 263 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 264 int board_mmc_getcd(struct mmc *mmc) 265 { 266 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 267 int ret = 0; 268 269 switch (cfg->esdhc_base) { 270 case USDHC2_BASE_ADDR: 271 ret = !gpio_get_value(USDHC2_CD_GPIO); 272 break; 273 case USDHC4_BASE_ADDR: 274 ret = 1; /* eMMC/uSDHC4 is always present */ 275 break; 276 } 277 278 return ret; 279 } 280 281 int board_mmc_init(bd_t *bd) 282 { 283 struct src *psrc = (struct src *)SRC_BASE_ADDR; 284 unsigned int reg = readl(&psrc->sbmr1) >> 11; 285 /* 286 * Upon reading BOOT_CFG register the following map is done: 287 * Bit 11 and 12 of BOOT_CFG register can determine the current 288 * mmc port 289 * 0x1 SD1 290 * 0x3 SD4 291 */ 292 293 switch (reg & 0x3) { 294 case 0x1: 295 SETUP_IOMUX_PADS(usdhc2_pads); 296 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 297 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 298 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 299 break; 300 case 0x3: 301 SETUP_IOMUX_PADS(usdhc4_pads); 302 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 303 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 304 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 305 break; 306 } 307 308 return fsl_esdhc_initialize(bd, &usdhc_cfg[0]); 309 } 310 311 void board_init_f(ulong dummy) 312 { 313 /* setup AIPS and disable watchdog */ 314 arch_cpu_init(); 315 316 ccgr_init(); 317 gpr_init(); 318 319 /* setup GP timer */ 320 timer_init(); 321 322 setup_iomux_sd(); 323 setup_iomux_uart(); 324 setup_iomux_usb(); 325 326 /* UART clocks enabled and gd valid - init serial console */ 327 preloader_console_init(); 328 329 /* DDR initialization */ 330 spl_dram_init(); 331 332 /* Clear the BSS. */ 333 memset(__bss_start, 0, __bss_end - __bss_start); 334 335 /* load/boot image from boot device */ 336 board_init_r(NULL, 0); 337 } 338