1 /* 2 * K+P iMX6Q KP_IMX6Q_TPC board configuration 3 * 4 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/io.h> 18 #include <asm/mach-imx/boot_mode.h> 19 #include <asm/mach-imx/iomux-v3.h> 20 #include <asm/mach-imx/mxc_i2c.h> 21 #include <errno.h> 22 #include <fsl_esdhc.h> 23 #include <fuse.h> 24 #include <i2c.h> 25 #include <miiphy.h> 26 #include <mmc.h> 27 #include <net.h> 28 #include <netdev.h> 29 #include <usb.h> 30 #include <usb/ehci-ci.h> 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #define ENET_PAD_CTRL \ 35 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 36 PAD_CTL_HYS) 37 38 #define I2C_PAD_CTRL \ 39 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 40 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) 41 42 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 43 44 static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = { 45 .scl = { 46 .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC, 47 .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC, 48 .gp = IMX_GPIO_NR(5, 27) 49 }, 50 .sda = { 51 .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC, 52 .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC, 53 .gp = IMX_GPIO_NR(5, 26) 54 } 55 }; 56 57 static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = { 58 .scl = { 59 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, 60 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, 61 .gp = IMX_GPIO_NR(4, 12) 62 }, 63 .sda = { 64 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, 65 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, 66 .gp = IMX_GPIO_NR(4, 13) 67 } 68 }; 69 70 int dram_init(void) 71 { 72 gd->ram_size = imx_ddr_size(); 73 return 0; 74 } 75 76 /* 77 * Do not overwrite the console 78 * Use always serial for U-Boot console 79 */ 80 int overwrite_console(void) 81 { 82 return 1; 83 } 84 85 #ifdef CONFIG_FEC_MXC 86 static iomux_v3_cfg_t const enet_pads[] = { 87 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 88 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 89 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 90 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 91 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 92 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 93 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 94 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | 95 MUX_PAD_CTRL(ENET_PAD_CTRL)), 96 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), 97 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 98 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 99 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 100 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 101 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 102 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | 103 MUX_PAD_CTRL(ENET_PAD_CTRL)), 104 /* AR8031 PHY Reset */ 105 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), 106 }; 107 108 static void eth_phy_reset(void) 109 { 110 /* Reset AR8031 PHY */ 111 gpio_direction_output(IMX_GPIO_NR(1, 25), 0); 112 mdelay(10); 113 gpio_set_value(IMX_GPIO_NR(1, 25), 1); 114 udelay(100); 115 } 116 117 static int setup_fec_clock(void) 118 { 119 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 120 121 /* set gpr1[21] to select anatop clock */ 122 clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21); 123 124 return enable_fec_anatop_clock(0, ENET_50MHZ); 125 } 126 127 int board_eth_init(bd_t *bis) 128 { 129 SETUP_IOMUX_PADS(enet_pads); 130 setup_fec_clock(); 131 eth_phy_reset(); 132 133 return cpu_eth_init(bis); 134 } 135 136 static int ar8031_phy_fixup(struct phy_device *phydev) 137 { 138 unsigned short val; 139 140 /* To enable AR8031 output a 125MHz clk from CLK_25M */ 141 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 142 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 143 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 144 145 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 146 val &= 0xffe3; 147 val |= 0x18; 148 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 149 150 /* introduce tx clock delay */ 151 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 152 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 153 val |= 0x0100; 154 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 155 156 return 0; 157 } 158 159 int board_phy_config(struct phy_device *phydev) 160 { 161 ar8031_phy_fixup(phydev); 162 163 if (phydev->drv->config) 164 phydev->drv->config(phydev); 165 166 return 0; 167 } 168 #endif 169 170 #ifdef CONFIG_FSL_ESDHC 171 172 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 173 static struct fsl_esdhc_cfg usdhc_cfg[] = { 174 { USDHC2_BASE_ADDR }, 175 { USDHC4_BASE_ADDR }, 176 }; 177 178 int board_mmc_getcd(struct mmc *mmc) 179 { 180 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 181 182 switch (cfg->esdhc_base) { 183 case USDHC2_BASE_ADDR: 184 return !gpio_get_value(USDHC2_CD_GPIO); 185 case USDHC4_BASE_ADDR: 186 return 1; /* eMMC/uSDHC4 is always present */ 187 } 188 189 return 0; 190 } 191 192 int board_mmc_init(bd_t *bis) 193 { 194 int i, ret; 195 196 /* 197 * According to the board_mmc_init() the following map is done: 198 * (U-Boot device node) (Physical Port) 199 * mmc0 micro SD 200 * mmc2 eMMC 201 */ 202 gpio_direction_input(USDHC2_CD_GPIO); 203 204 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 205 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 206 207 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 208 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 209 if (ret) 210 return ret; 211 } 212 213 return 0; 214 } 215 #endif 216 217 #ifdef CONFIG_USB_EHCI_MX6 218 static void setup_usb(void) 219 { 220 /* 221 * Set daisy chain for otg_pin_id on MX6Q. 222 * For MX6DL, this bit is reserved. 223 */ 224 imx_iomux_set_gpr_register(1, 13, 1, 0); 225 } 226 227 int board_usb_phy_mode(int port) 228 { 229 if (port == 1) 230 return USB_INIT_HOST; 231 else 232 return USB_INIT_DEVICE; 233 } 234 235 int board_ehci_power(int port, int on) 236 { 237 switch (port) { 238 case 0: 239 break; 240 case 1: 241 gpio_direction_output(IMX_GPIO_NR(3, 31), !!on); 242 break; 243 default: 244 printf("MXC USB port %d not yet supported\n", port); 245 return -EINVAL; 246 } 247 248 return 0; 249 } 250 #endif 251 252 int board_early_init_f(void) 253 { 254 #ifdef CONFIG_USB_EHCI_MX6 255 setup_usb(); 256 #endif 257 258 return 0; 259 } 260 261 int board_init(void) 262 { 263 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 264 265 /* address of boot parameters */ 266 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 267 268 /* Enable eim_slow clocks */ 269 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); 270 271 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0); 272 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1); 273 274 return 0; 275 } 276 277 #ifdef CONFIG_CMD_BMODE 278 static const struct boot_mode board_boot_modes[] = { 279 /* 4 bit bus width */ 280 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 281 /* 8 bit bus width */ 282 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, 283 {NULL, 0}, 284 }; 285 #endif 286 287 int board_late_init(void) 288 { 289 #ifdef CONFIG_CMD_BMODE 290 add_board_boot_modes(board_boot_modes); 291 #endif 292 293 env_set("boardname", "kp-tpc"); 294 env_set("boardsoc", "imx6q"); 295 return 0; 296 } 297 298 int checkboard(void) 299 { 300 puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n"); 301 return 0; 302 } 303