1 /* 2 * Copyright (C) 2018 3 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/iomux-mx53.h> 15 #include <asm/arch/clock.h> 16 #include <asm/gpio.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <power/pmic.h> 20 #include <fsl_pmic.h> 21 #include "kp_id_rev.h" 22 23 #define VBUS_PWR_EN IMX_GPIO_NR(7, 8) 24 #define PHY_nRST IMX_GPIO_NR(7, 6) 25 #define BOOSTER_OFF IMX_GPIO_NR(2, 23) 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 int dram_init(void) 30 { 31 u32 size; 32 33 size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 34 gd->ram_size = size; 35 36 return 0; 37 } 38 39 int dram_init_banksize(void) 40 { 41 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 42 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 43 44 return 0; 45 } 46 47 u32 get_board_rev(void) 48 { 49 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 50 struct fuse_bank *bank = &iim->bank[0]; 51 struct fuse_bank0_regs *fuse = 52 (struct fuse_bank0_regs *)bank->fuse_regs; 53 54 int rev = readl(&fuse->gp[6]); 55 56 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 57 } 58 59 #ifdef CONFIG_USB_EHCI_MX5 60 int board_ehci_hcd_init(int port) 61 { 62 gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN"); 63 gpio_direction_output(VBUS_PWR_EN, 1); 64 return 0; 65 } 66 #endif 67 68 #ifdef CONFIG_FSL_ESDHC 69 struct fsl_esdhc_cfg esdhc_cfg[] = { 70 {MMC_SDHC3_BASE_ADDR}, 71 }; 72 73 int board_mmc_getcd(struct mmc *mmc) 74 { 75 return 1; /* eMMC is always present */ 76 } 77 78 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 79 PAD_CTL_PUS_100K_UP) 80 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 81 PAD_CTL_DSE_HIGH) 82 83 int board_mmc_init(bd_t *bis) 84 { 85 int ret; 86 87 static const iomux_v3_cfg_t sd3_pads[] = { 88 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, 89 SD_CMD_PAD_CTRL), 90 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), 91 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), 92 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), 93 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), 94 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), 95 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), 96 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), 97 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), 98 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), 99 }; 100 101 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 102 imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); 103 104 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 105 if (ret) 106 return ret; 107 108 return 0; 109 } 110 #endif 111 112 static int power_init(void) 113 { 114 struct udevice *dev; 115 int ret; 116 117 ret = pmic_get("mc34708", &dev); 118 if (ret) { 119 printf("%s: mc34708 not found !\n", __func__); 120 return ret; 121 } 122 123 /* Set VDDGP to 1.110V for 800 MHz on SW1 */ 124 pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708, 125 SWx_1_110V_MC34708); 126 127 /* Set VCC as 1.30V on SW2 */ 128 pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708, 129 SWx_1_300V_MC34708); 130 131 /* Set global reset timer to 4s */ 132 pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708, 133 TIMER_4S_MC34708); 134 135 return ret; 136 } 137 138 static void setup_clocks(void) 139 { 140 int ret; 141 u32 ref_clk = MXC_HCLK; 142 /* 143 * CPU clock set to 800MHz and DDR to 400MHz 144 */ 145 ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK); 146 if (ret) 147 printf("CPU: Switch CPU clock to 800MHZ failed\n"); 148 149 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 150 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 151 if (ret) 152 printf("CPU: Switch DDR clock to 400MHz failed\n"); 153 } 154 155 static void setup_ups(void) 156 { 157 gpio_request(BOOSTER_OFF, "BOOSTER_OFF"); 158 gpio_direction_output(BOOSTER_OFF, 0); 159 } 160 161 int board_early_init_f(void) 162 { 163 return 0; 164 } 165 166 /* 167 * Do not overwrite the console 168 * Use always serial for U-Boot console 169 */ 170 int overwrite_console(void) 171 { 172 return 1; 173 } 174 175 int board_init(void) 176 { 177 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 178 179 return 0; 180 } 181 182 void eth_phy_reset(void) 183 { 184 gpio_request(PHY_nRST, "PHY_nRST"); 185 gpio_direction_output(PHY_nRST, 1); 186 udelay(50); 187 gpio_set_value(PHY_nRST, 0); 188 udelay(400); 189 gpio_set_value(PHY_nRST, 1); 190 udelay(50); 191 } 192 193 int board_late_init(void) 194 { 195 int ret = 0; 196 197 setup_ups(); 198 199 if (!power_init()) 200 setup_clocks(); 201 202 ret = read_eeprom(); 203 if (ret) 204 printf("Error %d reading EEPROM content!\n", ret); 205 206 eth_phy_reset(); 207 208 show_eeprom(); 209 read_board_id(); 210 211 return ret; 212 } 213