1 /* 2 * K+P iMX6Q KP_IMX6Q_TPC board configuration 3 * 4 * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/mx6-ddr.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/mach-imx/boot_mode.h> 19 #include <asm/mach-imx/iomux-v3.h> 20 #include <asm/mach-imx/mxc_i2c.h> 21 #include <asm/io.h> 22 #include <errno.h> 23 #include <fuse.h> 24 #include <fsl_esdhc.h> 25 #include <i2c.h> 26 #include <mmc.h> 27 #include <spl.h> 28 29 #define UART_PAD_CTRL \ 30 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 31 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 32 33 #define USDHC_PAD_CTRL \ 34 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 35 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 static void ccgr_init(void) 40 { 41 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 42 43 writel(0x00C03F3F, &ccm->CCGR0); 44 writel(0x0030FC03, &ccm->CCGR1); 45 writel(0x0FFFC000, &ccm->CCGR2); 46 writel(0x3FF00000, &ccm->CCGR3); 47 writel(0x00FFF300, &ccm->CCGR4); 48 writel(0x0F0000C3, &ccm->CCGR5); 49 writel(0x000003FF, &ccm->CCGR6); 50 } 51 52 /* onboard microSD */ 53 static iomux_v3_cfg_t const usdhc2_pads[] = { 54 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 55 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 56 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 57 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 58 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 59 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 60 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), 61 }; 62 63 /* eMMC */ 64 static iomux_v3_cfg_t const usdhc4_pads[] = { 65 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 66 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 67 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 68 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 69 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 70 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 71 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 72 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 73 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 74 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 75 }; 76 77 /* SD */ 78 static void setup_iomux_sd(void) 79 { 80 SETUP_IOMUX_PADS(usdhc2_pads); 81 SETUP_IOMUX_PADS(usdhc4_pads); 82 } 83 84 /* UART */ 85 static iomux_v3_cfg_t const uart1_pads[] = { 86 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 87 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 88 }; 89 90 static void setup_iomux_uart(void) 91 { 92 SETUP_IOMUX_PADS(uart1_pads); 93 } 94 95 /* USB */ 96 static iomux_v3_cfg_t const usb_pads[] = { 97 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), 98 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), 99 }; 100 101 static void setup_iomux_usb(void) 102 { 103 SETUP_IOMUX_PADS(usb_pads); 104 } 105 106 /* DDR3 */ 107 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { 108 .dram_sdclk_0 = 0x00000030, 109 .dram_sdclk_1 = 0x00000030, 110 .dram_cas = 0x00000030, 111 .dram_ras = 0x00000030, 112 .dram_reset = 0x00000030, 113 .dram_sdcke0 = 0x00003000, 114 .dram_sdcke1 = 0x00003000, 115 .dram_sdba2 = 0x00000000, 116 .dram_sdodt0 = 0x00000030, 117 .dram_sdodt1 = 0x00000030, 118 119 .dram_sdqs0 = 0x00000018, 120 .dram_sdqs1 = 0x00000018, 121 .dram_sdqs2 = 0x00000018, 122 .dram_sdqs3 = 0x00000018, 123 .dram_sdqs4 = 0x00000018, 124 .dram_sdqs5 = 0x00000018, 125 .dram_sdqs6 = 0x00000018, 126 .dram_sdqs7 = 0x00000018, 127 128 .dram_dqm0 = 0x00000018, 129 .dram_dqm1 = 0x00000018, 130 .dram_dqm2 = 0x00000018, 131 .dram_dqm3 = 0x00000018, 132 .dram_dqm4 = 0x00000018, 133 .dram_dqm5 = 0x00000018, 134 .dram_dqm6 = 0x00000018, 135 .dram_dqm7 = 0x00000018, 136 }; 137 138 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { 139 .grp_ddr_type = 0x000c0000, 140 .grp_ddrmode_ctl = 0x00020000, 141 .grp_ddrpke = 0x00000000, 142 .grp_addds = 0x00000030, 143 .grp_ctlds = 0x00000030, 144 .grp_ddrmode = 0x00020000, 145 .grp_b0ds = 0x00000018, 146 .grp_b1ds = 0x00000018, 147 .grp_b2ds = 0x00000018, 148 .grp_b3ds = 0x00000018, 149 .grp_b4ds = 0x00000018, 150 .grp_b5ds = 0x00000018, 151 .grp_b6ds = 0x00000018, 152 .grp_b7ds = 0x00000018, 153 }; 154 155 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { 156 .p0_mpwldectrl0 = 0x001F001F, 157 .p0_mpwldectrl1 = 0x001F001F, 158 .p1_mpwldectrl0 = 0x001F001F, 159 .p1_mpwldectrl1 = 0x001F001F, 160 .p0_mpdgctrl0 = 0x43270338, 161 .p0_mpdgctrl1 = 0x03200314, 162 .p1_mpdgctrl0 = 0x431A032F, 163 .p1_mpdgctrl1 = 0x03200263, 164 .p0_mprddlctl = 0x4B434748, 165 .p1_mprddlctl = 0x4445404C, 166 .p0_mpwrdlctl = 0x38444542, 167 .p1_mpwrdlctl = 0x4935493A, 168 }; 169 170 /* MT41K256M16 (4Gb density) */ 171 static const struct mx6_ddr3_cfg mt41k256m16 = { 172 .mem_speed = 1600, 173 .density = 4, 174 .width = 16, 175 .banks = 8, 176 .rowaddr = 15, 177 .coladdr = 10, 178 .pagesz = 2, 179 .trcd = 1375, 180 .trcmin = 4875, 181 .trasmin = 3500, 182 }; 183 184 #ifdef CONFIG_MX6_DDRCAL 185 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) 186 { 187 struct mx6_mmdc_calibration calibration = {0}; 188 189 mmdc_read_calibration(sysinfo, &calibration); 190 191 debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); 192 debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); 193 debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); 194 debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); 195 debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); 196 debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); 197 debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); 198 debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); 199 debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); 200 debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); 201 debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); 202 debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); 203 } 204 205 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) 206 { 207 int ret; 208 209 /* Perform DDR DRAM calibration */ 210 udelay(100); 211 ret = mmdc_do_write_level_calibration(sysinfo); 212 if (ret) { 213 printf("DDR: Write level calibration error [%d]\n", ret); 214 return; 215 } 216 217 ret = mmdc_do_dqs_calibration(sysinfo); 218 if (ret) { 219 printf("DDR: DQS calibration error [%d]\n", ret); 220 return; 221 } 222 223 spl_dram_print_cal(sysinfo); 224 } 225 #endif /* CONFIG_MX6_DDRCAL */ 226 227 static void spl_dram_init(void) 228 { 229 struct mx6_ddr_sysinfo sysinfo = { 230 /* width of data bus:0=16,1=32,2=64 */ 231 .dsize = 2, 232 /* config for full 4GB range so that get_mem_size() works */ 233 .cs_density = 32, /* 32Gb per CS */ 234 /* single chip select */ 235 .ncs = 1, 236 .cs1_mirror = 0, 237 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 238 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 239 .walat = 1, /* Write additional latency */ 240 .ralat = 5, /* Read additional latency */ 241 .mif3_mode = 3, /* Command prediction working mode */ 242 .bi_on = 1, /* Bank interleaving enabled */ 243 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 244 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 245 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 246 .ddr_type = DDR_TYPE_DDR3, 247 .refsel = 1, /* Refresh cycles at 32KHz */ 248 .refr = 7, /* 8 refresh commands per refresh cycle */ 249 }; 250 251 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); 252 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16); 253 254 #ifdef CONFIG_MX6_DDRCAL 255 spl_dram_perform_cal(&sysinfo); 256 #endif 257 } 258 259 struct fsl_esdhc_cfg usdhc_cfg[] = { 260 {USDHC2_BASE_ADDR}, 261 {USDHC4_BASE_ADDR}, 262 }; 263 264 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 265 int board_mmc_getcd(struct mmc *mmc) 266 { 267 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 268 int ret = 0; 269 270 switch (cfg->esdhc_base) { 271 case USDHC2_BASE_ADDR: 272 ret = !gpio_get_value(USDHC2_CD_GPIO); 273 break; 274 case USDHC4_BASE_ADDR: 275 ret = 1; /* eMMC/uSDHC4 is always present */ 276 break; 277 } 278 279 return ret; 280 } 281 282 int board_mmc_init(bd_t *bd) 283 { 284 struct src *psrc = (struct src *)SRC_BASE_ADDR; 285 unsigned int reg = readl(&psrc->sbmr1) >> 11; 286 /* 287 * Upon reading BOOT_CFG register the following map is done: 288 * Bit 11 and 12 of BOOT_CFG register can determine the current 289 * mmc port 290 * 0x1 SD1 291 * 0x3 SD4 292 */ 293 294 switch (reg & 0x3) { 295 case 0x1: 296 SETUP_IOMUX_PADS(usdhc2_pads); 297 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 298 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 299 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 300 break; 301 case 0x3: 302 SETUP_IOMUX_PADS(usdhc4_pads); 303 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; 304 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 305 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 306 break; 307 } 308 309 return fsl_esdhc_initialize(bd, &usdhc_cfg[0]); 310 } 311 312 void board_init_f(ulong dummy) 313 { 314 /* setup AIPS and disable watchdog */ 315 arch_cpu_init(); 316 317 ccgr_init(); 318 gpr_init(); 319 320 /* setup GP timer */ 321 timer_init(); 322 323 setup_iomux_sd(); 324 setup_iomux_uart(); 325 setup_iomux_usb(); 326 327 /* UART clocks enabled and gd valid - init serial console */ 328 preloader_console_init(); 329 330 /* DDR initialization */ 331 spl_dram_init(); 332 333 /* Clear the BSS. */ 334 memset(__bss_start, 0, __bss_end - __bss_start); 335 336 /* load/boot image from boot device */ 337 board_init_r(NULL, 0); 338 } 339