1 /* 2 * (C) Copyright 2010 3 * ISEE 2007 SL, <www.iseebcn.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <twl4030.h> 9 #include <netdev.h> 10 #include <asm/gpio.h> 11 #include <asm/io.h> 12 #include <asm/arch/mem.h> 13 #include <asm/arch/mmc_host_def.h> 14 #include <asm/arch/mux.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/mach-types.h> 17 #include "igep00x0.h" 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #if defined(CONFIG_CMD_NET) 22 /* GPMC definitions for LAN9221 chips */ 23 static const u32 gpmc_lan_config[] = { 24 NET_LAN9221_GPMC_CONFIG1, 25 NET_LAN9221_GPMC_CONFIG2, 26 NET_LAN9221_GPMC_CONFIG3, 27 NET_LAN9221_GPMC_CONFIG4, 28 NET_LAN9221_GPMC_CONFIG5, 29 NET_LAN9221_GPMC_CONFIG6, 30 }; 31 #endif 32 33 /* 34 * Routine: board_init 35 * Description: Early hardware init. 36 */ 37 int board_init(void) 38 { 39 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 40 /* boot param addr */ 41 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 42 43 return 0; 44 } 45 46 #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) 47 void show_boot_progress(int val) 48 { 49 if (val < 0) { 50 /* something went wrong */ 51 return; 52 } 53 54 if (!gpio_request(IGEP00X0_GPIO_LED, "")) 55 gpio_direction_output(IGEP00X0_GPIO_LED, 1); 56 } 57 #endif 58 59 #ifdef CONFIG_SPL_BUILD 60 /* 61 * Routine: omap_rev_string 62 * Description: For SPL builds output board rev 63 */ 64 void omap_rev_string(void) 65 { 66 } 67 68 /* 69 * Routine: get_board_mem_timings 70 * Description: If we use SPL then there is no x-loader nor config header 71 * so we have to setup the DDR timings ourself on both banks. 72 */ 73 void get_board_mem_timings(struct board_sdrc_timings *timings) 74 { 75 timings->mr = MICRON_V_MR_165; 76 #ifdef CONFIG_BOOT_NAND 77 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 78 timings->ctrla = MICRON_V_ACTIMA_200; 79 timings->ctrlb = MICRON_V_ACTIMB_200; 80 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 81 #else 82 if (get_cpu_family() == CPU_OMAP34XX) { 83 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 84 timings->ctrla = NUMONYX_V_ACTIMA_165; 85 timings->ctrlb = NUMONYX_V_ACTIMB_165; 86 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 87 88 } else { 89 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 90 timings->ctrla = NUMONYX_V_ACTIMA_200; 91 timings->ctrlb = NUMONYX_V_ACTIMB_200; 92 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 93 } 94 #endif 95 } 96 #endif 97 98 #if defined(CONFIG_CMD_NET) 99 /* 100 * Routine: setup_net_chip 101 * Description: Setting up the configuration GPMC registers specific to the 102 * Ethernet hardware. 103 */ 104 static void setup_net_chip(void) 105 { 106 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 107 108 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 109 GPMC_SIZE_16M); 110 111 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 112 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 113 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 114 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 115 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 116 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 117 &ctrl_base->gpmc_nadv_ale); 118 119 /* Make GPIO 64 as output pin and send a magic pulse through it */ 120 if (!gpio_request(64, "")) { 121 gpio_direction_output(64, 0); 122 gpio_set_value(64, 1); 123 udelay(1); 124 gpio_set_value(64, 0); 125 udelay(1); 126 gpio_set_value(64, 1); 127 } 128 } 129 #else 130 static inline void setup_net_chip(void) {} 131 #endif 132 133 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 134 int board_mmc_init(bd_t *bis) 135 { 136 return omap_mmc_init(0, 0, 0, -1, -1); 137 } 138 #endif 139 140 void set_fdt(void) 141 { 142 switch (gd->bd->bi_arch_number) { 143 case MACH_TYPE_IGEP0020: 144 setenv("dtbfile", "omap3-igep0020.dtb"); 145 break; 146 case MACH_TYPE_IGEP0030: 147 setenv("dtbfile", "omap3-igep0030.dtb"); 148 break; 149 } 150 } 151 152 /* 153 * Routine: misc_init_r 154 * Description: Configure board specific parts 155 */ 156 int misc_init_r(void) 157 { 158 twl4030_power_init(); 159 160 setup_net_chip(); 161 162 dieid_num_r(); 163 164 set_fdt(); 165 166 return 0; 167 } 168 169 /* 170 * Routine: set_muxconf_regs 171 * Description: Setting up the configuration Mux registers specific to the 172 * hardware. Many pins need to be moved from protect to primary 173 * mode. 174 */ 175 void set_muxconf_regs(void) 176 { 177 MUX_DEFAULT(); 178 179 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 180 MUX_IGEP0020(); 181 #endif 182 183 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 184 MUX_IGEP0030(); 185 #endif 186 } 187 188 #if defined(CONFIG_CMD_NET) 189 int board_eth_init(bd_t *bis) 190 { 191 int rc = 0; 192 #ifdef CONFIG_SMC911X 193 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 194 #endif 195 return rc; 196 } 197 #endif 198