1 /* 2 * (C) Copyright 2010 3 * ISEE 2007 SL, <www.iseebcn.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <common.h> 24 #include <twl4030.h> 25 #include <netdev.h> 26 #include <asm/gpio.h> 27 #include <asm/omap_gpmc.h> 28 #include <asm/io.h> 29 #include <asm/arch/mem.h> 30 #include <asm/arch/mmc_host_def.h> 31 #include <asm/arch/mux.h> 32 #include <asm/arch/sys_proto.h> 33 #include <asm/mach-types.h> 34 #include "igep00x0.h" 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #if defined(CONFIG_CMD_NET) 39 /* GPMC definitions for LAN9221 chips */ 40 static const u32 gpmc_lan_config[] = { 41 NET_LAN9221_GPMC_CONFIG1, 42 NET_LAN9221_GPMC_CONFIG2, 43 NET_LAN9221_GPMC_CONFIG3, 44 NET_LAN9221_GPMC_CONFIG4, 45 NET_LAN9221_GPMC_CONFIG5, 46 NET_LAN9221_GPMC_CONFIG6, 47 }; 48 #endif 49 50 /* 51 * Routine: board_init 52 * Description: Early hardware init. 53 */ 54 int board_init(void) 55 { 56 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 57 /* boot param addr */ 58 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 59 60 return 0; 61 } 62 63 #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) 64 void show_boot_progress(int val) 65 { 66 if (val < 0) { 67 /* something went wrong */ 68 return; 69 } 70 71 if (!gpio_request(IGEP00X0_GPIO_LED, "")) 72 gpio_direction_output(IGEP00X0_GPIO_LED, 1); 73 } 74 #endif 75 76 #ifdef CONFIG_SPL_BUILD 77 /* 78 * Routine: omap_rev_string 79 * Description: For SPL builds output board rev 80 */ 81 void omap_rev_string(void) 82 { 83 } 84 85 /* 86 * Routine: get_board_mem_timings 87 * Description: If we use SPL then there is no x-loader nor config header 88 * so we have to setup the DDR timings ourself on both banks. 89 */ 90 void get_board_mem_timings(struct board_sdrc_timings *timings) 91 { 92 timings->mr = MICRON_V_MR_165; 93 #ifdef CONFIG_BOOT_NAND 94 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 95 timings->ctrla = MICRON_V_ACTIMA_200; 96 timings->ctrlb = MICRON_V_ACTIMB_200; 97 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 98 #else 99 if (get_cpu_family() == CPU_OMAP34XX) { 100 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 101 timings->ctrla = NUMONYX_V_ACTIMA_165; 102 timings->ctrlb = NUMONYX_V_ACTIMB_165; 103 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 104 105 } else { 106 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 107 timings->ctrla = NUMONYX_V_ACTIMA_200; 108 timings->ctrlb = NUMONYX_V_ACTIMB_200; 109 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 110 } 111 #endif 112 } 113 #endif 114 115 #if defined(CONFIG_CMD_NET) 116 /* 117 * Routine: setup_net_chip 118 * Description: Setting up the configuration GPMC registers specific to the 119 * Ethernet hardware. 120 */ 121 static void setup_net_chip(void) 122 { 123 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 124 125 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 126 GPMC_SIZE_16M); 127 128 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 129 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 130 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 131 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 132 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 133 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 134 &ctrl_base->gpmc_nadv_ale); 135 136 /* Make GPIO 64 as output pin and send a magic pulse through it */ 137 if (!gpio_request(64, "")) { 138 gpio_direction_output(64, 0); 139 gpio_set_value(64, 1); 140 udelay(1); 141 gpio_set_value(64, 0); 142 udelay(1); 143 gpio_set_value(64, 1); 144 } 145 } 146 #else 147 static inline void setup_net_chip(void) {} 148 #endif 149 150 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 151 int board_mmc_init(bd_t *bis) 152 { 153 return omap_mmc_init(0, 0, 0, -1, -1); 154 } 155 #endif 156 157 /* 158 * Routine: misc_init_r 159 * Description: Configure board specific parts 160 */ 161 int misc_init_r(void) 162 { 163 twl4030_power_init(); 164 165 setup_net_chip(); 166 167 dieid_num_r(); 168 169 return 0; 170 } 171 172 /* 173 * Routine: set_muxconf_regs 174 * Description: Setting up the configuration Mux registers specific to the 175 * hardware. Many pins need to be moved from protect to primary 176 * mode. 177 */ 178 void set_muxconf_regs(void) 179 { 180 MUX_DEFAULT(); 181 182 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 183 MUX_IGEP0020(); 184 #endif 185 186 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 187 MUX_IGEP0030(); 188 #endif 189 } 190 191 #if defined(CONFIG_CMD_NET) 192 int board_eth_init(bd_t *bis) 193 { 194 int rc = 0; 195 #ifdef CONFIG_SMC911X 196 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 197 #endif 198 return rc; 199 } 200 #endif 201