xref: /openbmc/u-boot/board/isee/igep00x0/igep00x0.c (revision 55ed3b46) 
1 /*
2  * (C) Copyright 2010
3  * ISEE 2007 SL, <www.iseebcn.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 #include <common.h>
8 #include <status_led.h>
9 #include <dm.h>
10 #include <ns16550.h>
11 #include <twl4030.h>
12 #include <netdev.h>
13 #include <spl.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <asm/arch/mem.h>
17 #include <asm/arch/mmc_host_def.h>
18 #include <asm/arch/mux.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-types.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/nand.h>
24 #include <linux/mtd/onenand.h>
25 #include <jffs2/load_kernel.h>
26 #include "igep00x0.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 static const struct ns16550_platdata igep_serial = {
31 	.base = OMAP34XX_UART3,
32 	.reg_shift = 2,
33 	.clock = V_NS16550_CLK
34 };
35 
36 U_BOOT_DEVICE(igep_uart) = {
37 	"ns16550_serial",
38 	&igep_serial
39 };
40 
41 /*
42  * Routine: board_init
43  * Description: Early hardware init.
44  */
45 int board_init(void)
46 {
47 	int loops = 100;
48 
49 	/* find out flash memory type, assume NAND first */
50 	gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
51 	gpmc_init();
52 
53 	/* Issue a RESET and then READID */
54 	writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
55 	writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
56 	while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
57 	                                        != NAND_STATUS_READY) {
58 		udelay(1);
59 		if (--loops == 0) {
60 			gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
61 			gpmc_init();	/* reinitialize for OneNAND */
62 			break;
63 		}
64 	}
65 
66 	/* boot param addr */
67 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
68 
69 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
70 	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
71 #endif
72 
73 	return 0;
74 }
75 
76 #ifdef CONFIG_SPL_BUILD
77 /*
78  * Routine: get_board_mem_timings
79  * Description: If we use SPL then there is no x-loader nor config header
80  * so we have to setup the DDR timings ourself on both banks.
81  */
82 void get_board_mem_timings(struct board_sdrc_timings *timings)
83 {
84 	int mfr, id, err = identify_nand_chip(&mfr, &id);
85 
86 	timings->mr = MICRON_V_MR_165;
87 	if (!err) {
88 		switch (mfr) {
89 		case NAND_MFR_HYNIX:
90 			timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
91 			timings->ctrla = HYNIX_V_ACTIMA_200;
92 			timings->ctrlb = HYNIX_V_ACTIMB_200;
93 			break;
94 		case NAND_MFR_MICRON:
95 			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
96 			timings->ctrla = MICRON_V_ACTIMA_200;
97 			timings->ctrlb = MICRON_V_ACTIMB_200;
98 			break;
99 		default:
100 			/* Should not happen... */
101 			break;
102 		}
103 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
104 		gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
105 	} else {
106 		if (get_cpu_family() == CPU_OMAP34XX) {
107 			timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
108 			timings->ctrla = NUMONYX_V_ACTIMA_165;
109 			timings->ctrlb = NUMONYX_V_ACTIMB_165;
110 			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
111 		} else {
112 			timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
113 			timings->ctrla = NUMONYX_V_ACTIMA_200;
114 			timings->ctrlb = NUMONYX_V_ACTIMB_200;
115 			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
116 		}
117 		gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
118 	}
119 }
120 
121 #ifdef CONFIG_SPL_OS_BOOT
122 int spl_start_uboot(void)
123 {
124 	/* break into full u-boot on 'c' */
125 	if (serial_tstc() && serial_getc() == 'c')
126 		return 1;
127 
128 	return 0;
129 }
130 #endif
131 #endif
132 
133 int onenand_board_init(struct mtd_info *mtd)
134 {
135 	if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
136 		struct onenand_chip *this = mtd->priv;
137 		this->base = (void *)CONFIG_SYS_ONENAND_BASE;
138 		return 0;
139 	}
140 	return 1;
141 }
142 
143 #if defined(CONFIG_CMD_NET)
144 static void reset_net_chip(int gpio)
145 {
146 	if (!gpio_request(gpio, "eth nrst")) {
147 		gpio_direction_output(gpio, 1);
148 		udelay(1);
149 		gpio_set_value(gpio, 0);
150 		udelay(40);
151 		gpio_set_value(gpio, 1);
152 		mdelay(10);
153 	}
154 }
155 
156 /*
157  * Routine: setup_net_chip
158  * Description: Setting up the configuration GPMC registers specific to the
159  *		Ethernet hardware.
160  */
161 static void setup_net_chip(void)
162 {
163 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
164 	static const u32 gpmc_lan_config[] = {
165 		NET_LAN9221_GPMC_CONFIG1,
166 		NET_LAN9221_GPMC_CONFIG2,
167 		NET_LAN9221_GPMC_CONFIG3,
168 		NET_LAN9221_GPMC_CONFIG4,
169 		NET_LAN9221_GPMC_CONFIG5,
170 		NET_LAN9221_GPMC_CONFIG6,
171 	};
172 
173 	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
174 			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
175 
176 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
177 	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
178 	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
179 	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
180 	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
181 	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
182 		&ctrl_base->gpmc_nadv_ale);
183 
184 	reset_net_chip(64);
185 }
186 
187 int board_eth_init(bd_t *bis)
188 {
189 #ifdef CONFIG_SMC911X
190 	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
191 #else
192 	return 0;
193 #endif
194 }
195 #else
196 static inline void setup_net_chip(void) {}
197 #endif
198 
199 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
200 int board_mmc_init(bd_t *bis)
201 {
202 	return omap_mmc_init(0, 0, 0, -1, -1);
203 }
204 #endif
205 
206 #if defined(CONFIG_GENERIC_MMC)
207 void board_mmc_power_init(void)
208 {
209 	twl4030_power_mmc_init(0);
210 }
211 #endif
212 
213 void set_fdt(void)
214 {
215 	switch (gd->bd->bi_arch_number) {
216 	case MACH_TYPE_IGEP0020:
217 		setenv("fdtfile", "omap3-igep0020.dtb");
218 		break;
219 	case MACH_TYPE_IGEP0030:
220 		setenv("fdtfile", "omap3-igep0030.dtb");
221 		break;
222 	}
223 }
224 
225 /*
226  * Routine: misc_init_r
227  * Description: Configure board specific parts
228  */
229 int misc_init_r(void)
230 {
231 	twl4030_power_init();
232 
233 	setup_net_chip();
234 
235 	omap_die_id_display();
236 
237 	set_fdt();
238 
239 	return 0;
240 }
241 
242 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
243 {
244 	struct mtd_info *mtd = get_mtd_device(NULL, 0);
245 	if (mtd) {
246 		static char ids[24];
247 		static char parts[48];
248 		const char *linux_name = "omap2-nand";
249 		if (strncmp(mtd->name, "onenand0", 8) == 0)
250 			linux_name = "omap2-onenand";
251 		snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
252 		snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
253 		         linux_name, 4 * mtd->erasesize >> 10);
254 		*mtdids = ids;
255 		*mtdparts = parts;
256 	}
257 }
258 
259 /*
260  * Routine: set_muxconf_regs
261  * Description: Setting up the configuration Mux registers specific to the
262  *		hardware. Many pins need to be moved from protect to primary
263  *		mode.
264  */
265 void set_muxconf_regs(void)
266 {
267 	MUX_DEFAULT();
268 
269 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
270 	MUX_IGEP0020();
271 #endif
272 
273 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
274 	MUX_IGEP0030();
275 #endif
276 }
277