1 /* 2 * (C) Copyright 2010 3 * ISEE 2007 SL, <www.iseebcn.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <dm.h> 9 #include <ns16550.h> 10 #include <twl4030.h> 11 #include <netdev.h> 12 #include <asm/gpio.h> 13 #include <asm/io.h> 14 #include <asm/arch/mem.h> 15 #include <asm/arch/mmc_host_def.h> 16 #include <asm/arch/mux.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/mach-types.h> 19 #include "igep00x0.h" 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 #if defined(CONFIG_CMD_NET) 24 /* GPMC definitions for LAN9221 chips */ 25 static const u32 gpmc_lan_config[] = { 26 NET_LAN9221_GPMC_CONFIG1, 27 NET_LAN9221_GPMC_CONFIG2, 28 NET_LAN9221_GPMC_CONFIG3, 29 NET_LAN9221_GPMC_CONFIG4, 30 NET_LAN9221_GPMC_CONFIG5, 31 NET_LAN9221_GPMC_CONFIG6, 32 }; 33 #endif 34 35 static const struct ns16550_platdata igep_serial = { 36 OMAP34XX_UART3, 37 2, 38 V_NS16550_CLK 39 }; 40 41 U_BOOT_DEVICE(igep_uart) = { 42 "serial_omap", 43 &igep_serial 44 }; 45 46 /* 47 * Routine: board_init 48 * Description: Early hardware init. 49 */ 50 int board_init(void) 51 { 52 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 53 /* boot param addr */ 54 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 55 56 return 0; 57 } 58 59 #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) 60 void show_boot_progress(int val) 61 { 62 if (val < 0) { 63 /* something went wrong */ 64 return; 65 } 66 67 if (!gpio_request(IGEP00X0_GPIO_LED, "")) 68 gpio_direction_output(IGEP00X0_GPIO_LED, 1); 69 } 70 #endif 71 72 #ifdef CONFIG_SPL_BUILD 73 /* 74 * Routine: omap_rev_string 75 * Description: For SPL builds output board rev 76 */ 77 void omap_rev_string(void) 78 { 79 } 80 81 /* 82 * Routine: get_board_mem_timings 83 * Description: If we use SPL then there is no x-loader nor config header 84 * so we have to setup the DDR timings ourself on both banks. 85 */ 86 void get_board_mem_timings(struct board_sdrc_timings *timings) 87 { 88 timings->mr = MICRON_V_MR_165; 89 #ifdef CONFIG_BOOT_NAND 90 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 91 timings->ctrla = MICRON_V_ACTIMA_200; 92 timings->ctrlb = MICRON_V_ACTIMB_200; 93 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 94 #else 95 if (get_cpu_family() == CPU_OMAP34XX) { 96 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 97 timings->ctrla = NUMONYX_V_ACTIMA_165; 98 timings->ctrlb = NUMONYX_V_ACTIMB_165; 99 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 100 101 } else { 102 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 103 timings->ctrla = NUMONYX_V_ACTIMA_200; 104 timings->ctrlb = NUMONYX_V_ACTIMB_200; 105 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 106 } 107 #endif 108 } 109 #endif 110 111 #if defined(CONFIG_CMD_NET) 112 /* 113 * Routine: setup_net_chip 114 * Description: Setting up the configuration GPMC registers specific to the 115 * Ethernet hardware. 116 */ 117 static void setup_net_chip(void) 118 { 119 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 120 121 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 122 GPMC_SIZE_16M); 123 124 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 125 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 126 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 127 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 128 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 129 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 130 &ctrl_base->gpmc_nadv_ale); 131 132 /* Make GPIO 64 as output pin and send a magic pulse through it */ 133 if (!gpio_request(64, "")) { 134 gpio_direction_output(64, 0); 135 gpio_set_value(64, 1); 136 udelay(1); 137 gpio_set_value(64, 0); 138 udelay(1); 139 gpio_set_value(64, 1); 140 } 141 } 142 #else 143 static inline void setup_net_chip(void) {} 144 #endif 145 146 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 147 int board_mmc_init(bd_t *bis) 148 { 149 return omap_mmc_init(0, 0, 0, -1, -1); 150 } 151 #endif 152 153 #if defined(CONFIG_GENERIC_MMC) 154 void board_mmc_power_init(void) 155 { 156 twl4030_power_mmc_init(0); 157 } 158 #endif 159 160 void set_fdt(void) 161 { 162 switch (gd->bd->bi_arch_number) { 163 case MACH_TYPE_IGEP0020: 164 setenv("dtbfile", "omap3-igep0020.dtb"); 165 break; 166 case MACH_TYPE_IGEP0030: 167 setenv("dtbfile", "omap3-igep0030.dtb"); 168 break; 169 } 170 } 171 172 /* 173 * Routine: misc_init_r 174 * Description: Configure board specific parts 175 */ 176 int misc_init_r(void) 177 { 178 twl4030_power_init(); 179 180 setup_net_chip(); 181 182 dieid_num_r(); 183 184 set_fdt(); 185 186 return 0; 187 } 188 189 /* 190 * Routine: set_muxconf_regs 191 * Description: Setting up the configuration Mux registers specific to the 192 * hardware. Many pins need to be moved from protect to primary 193 * mode. 194 */ 195 void set_muxconf_regs(void) 196 { 197 MUX_DEFAULT(); 198 199 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 200 MUX_IGEP0020(); 201 #endif 202 203 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 204 MUX_IGEP0030(); 205 #endif 206 } 207 208 #if defined(CONFIG_CMD_NET) 209 int board_eth_init(bd_t *bis) 210 { 211 int rc = 0; 212 #ifdef CONFIG_SMC911X 213 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 214 #endif 215 return rc; 216 } 217 #endif 218