1 /* 2 * (C) Copyright 2010 3 * ISEE 2007 SL, <www.iseebcn.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 #include <common.h> 8 #include <twl4030.h> 9 #include <netdev.h> 10 #include <asm/gpio.h> 11 #include <asm/omap_gpmc.h> 12 #include <asm/io.h> 13 #include <asm/arch/mem.h> 14 #include <asm/arch/mmc_host_def.h> 15 #include <asm/arch/mux.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/mach-types.h> 18 #include "igep00x0.h" 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #if defined(CONFIG_CMD_NET) 23 /* GPMC definitions for LAN9221 chips */ 24 static const u32 gpmc_lan_config[] = { 25 NET_LAN9221_GPMC_CONFIG1, 26 NET_LAN9221_GPMC_CONFIG2, 27 NET_LAN9221_GPMC_CONFIG3, 28 NET_LAN9221_GPMC_CONFIG4, 29 NET_LAN9221_GPMC_CONFIG5, 30 NET_LAN9221_GPMC_CONFIG6, 31 }; 32 #endif 33 34 /* 35 * Routine: board_init 36 * Description: Early hardware init. 37 */ 38 int board_init(void) 39 { 40 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 41 /* boot param addr */ 42 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 43 44 return 0; 45 } 46 47 #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) 48 void show_boot_progress(int val) 49 { 50 if (val < 0) { 51 /* something went wrong */ 52 return; 53 } 54 55 if (!gpio_request(IGEP00X0_GPIO_LED, "")) 56 gpio_direction_output(IGEP00X0_GPIO_LED, 1); 57 } 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 /* 62 * Routine: omap_rev_string 63 * Description: For SPL builds output board rev 64 */ 65 void omap_rev_string(void) 66 { 67 } 68 69 /* 70 * Routine: get_board_mem_timings 71 * Description: If we use SPL then there is no x-loader nor config header 72 * so we have to setup the DDR timings ourself on both banks. 73 */ 74 void get_board_mem_timings(struct board_sdrc_timings *timings) 75 { 76 timings->mr = MICRON_V_MR_165; 77 #ifdef CONFIG_BOOT_NAND 78 timings->mcfg = MICRON_V_MCFG_200(256 << 20); 79 timings->ctrla = MICRON_V_ACTIMA_200; 80 timings->ctrlb = MICRON_V_ACTIMB_200; 81 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 82 #else 83 if (get_cpu_family() == CPU_OMAP34XX) { 84 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 85 timings->ctrla = NUMONYX_V_ACTIMA_165; 86 timings->ctrlb = NUMONYX_V_ACTIMB_165; 87 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 88 89 } else { 90 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 91 timings->ctrla = NUMONYX_V_ACTIMA_200; 92 timings->ctrlb = NUMONYX_V_ACTIMB_200; 93 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 94 } 95 #endif 96 } 97 #endif 98 99 #if defined(CONFIG_CMD_NET) 100 /* 101 * Routine: setup_net_chip 102 * Description: Setting up the configuration GPMC registers specific to the 103 * Ethernet hardware. 104 */ 105 static void setup_net_chip(void) 106 { 107 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 108 109 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 110 GPMC_SIZE_16M); 111 112 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 113 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 114 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 115 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 116 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 117 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 118 &ctrl_base->gpmc_nadv_ale); 119 120 /* Make GPIO 64 as output pin and send a magic pulse through it */ 121 if (!gpio_request(64, "")) { 122 gpio_direction_output(64, 0); 123 gpio_set_value(64, 1); 124 udelay(1); 125 gpio_set_value(64, 0); 126 udelay(1); 127 gpio_set_value(64, 1); 128 } 129 } 130 #else 131 static inline void setup_net_chip(void) {} 132 #endif 133 134 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 135 int board_mmc_init(bd_t *bis) 136 { 137 return omap_mmc_init(0, 0, 0, -1, -1); 138 } 139 #endif 140 141 void set_fdt(void) 142 { 143 switch (gd->bd->bi_arch_number) { 144 case MACH_TYPE_IGEP0020: 145 setenv("dtbfile", "omap3-igep0020.dtb"); 146 break; 147 case MACH_TYPE_IGEP0030: 148 setenv("dtbfile", "omap3-igep0030.dtb"); 149 break; 150 } 151 } 152 153 /* 154 * Routine: misc_init_r 155 * Description: Configure board specific parts 156 */ 157 int misc_init_r(void) 158 { 159 twl4030_power_init(); 160 161 setup_net_chip(); 162 163 dieid_num_r(); 164 165 set_fdt(); 166 167 return 0; 168 } 169 170 /* 171 * Routine: set_muxconf_regs 172 * Description: Setting up the configuration Mux registers specific to the 173 * hardware. Many pins need to be moved from protect to primary 174 * mode. 175 */ 176 void set_muxconf_regs(void) 177 { 178 MUX_DEFAULT(); 179 180 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 181 MUX_IGEP0020(); 182 #endif 183 184 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 185 MUX_IGEP0030(); 186 #endif 187 } 188 189 #if defined(CONFIG_CMD_NET) 190 int board_eth_init(bd_t *bis) 191 { 192 int rc = 0; 193 #ifdef CONFIG_SMC911X 194 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 195 #endif 196 return rc; 197 } 198 #endif 199