177eea280SJavier Martinez Canillas /* 277eea280SJavier Martinez Canillas * (C) Copyright 2010 377eea280SJavier Martinez Canillas * ISEE 2007 SL, <www.iseebcn.com> 477eea280SJavier Martinez Canillas * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 677eea280SJavier Martinez Canillas */ 777eea280SJavier Martinez Canillas #include <common.h> 8f3b4bc45SEnric Balletbo i Serra #include <status_led.h> 9b3f4ca11SSimon Glass #include <dm.h> 10b3f4ca11SSimon Glass #include <ns16550.h> 1177eea280SJavier Martinez Canillas #include <twl4030.h> 1277eea280SJavier Martinez Canillas #include <netdev.h> 1377eea280SJavier Martinez Canillas #include <asm/gpio.h> 1477eea280SJavier Martinez Canillas #include <asm/io.h> 1577eea280SJavier Martinez Canillas #include <asm/arch/mem.h> 1677eea280SJavier Martinez Canillas #include <asm/arch/mmc_host_def.h> 1777eea280SJavier Martinez Canillas #include <asm/arch/mux.h> 1877eea280SJavier Martinez Canillas #include <asm/arch/sys_proto.h> 1977eea280SJavier Martinez Canillas #include <asm/mach-types.h> 2077eea280SJavier Martinez Canillas #include "igep00x0.h" 2177eea280SJavier Martinez Canillas 2277eea280SJavier Martinez Canillas DECLARE_GLOBAL_DATA_PTR; 2377eea280SJavier Martinez Canillas 24b7e042d6SLadislav Michl const omap3_sysinfo sysinfo = { 25b7e042d6SLadislav Michl DDR_STACKED, 26b7e042d6SLadislav Michl #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 27b7e042d6SLadislav Michl "IGEPv2", 28b7e042d6SLadislav Michl #endif 29b7e042d6SLadislav Michl #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 30b7e042d6SLadislav Michl "IGEP COM MODULE/ELECTRON", 31b7e042d6SLadislav Michl #endif 32b7e042d6SLadislav Michl #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) 33b7e042d6SLadislav Michl "IGEP COM PROTON", 34b7e042d6SLadislav Michl #endif 35b7e042d6SLadislav Michl #if defined(CONFIG_ENV_IS_IN_ONENAND) 36b7e042d6SLadislav Michl "ONENAND", 37b7e042d6SLadislav Michl #else 38b7e042d6SLadislav Michl "NAND", 39b7e042d6SLadislav Michl #endif 40b7e042d6SLadislav Michl }; 41b7e042d6SLadislav Michl 42b3f4ca11SSimon Glass static const struct ns16550_platdata igep_serial = { 432f6ed3b8SAdam Ford .base = OMAP34XX_UART3, 442f6ed3b8SAdam Ford .reg_shift = 2, 452f6ed3b8SAdam Ford .clock = V_NS16550_CLK 46b3f4ca11SSimon Glass }; 47b3f4ca11SSimon Glass 48b3f4ca11SSimon Glass U_BOOT_DEVICE(igep_uart) = { 49c7b9686dSThomas Chou "ns16550_serial", 50b3f4ca11SSimon Glass &igep_serial 51b3f4ca11SSimon Glass }; 52b3f4ca11SSimon Glass 5377eea280SJavier Martinez Canillas /* 5477eea280SJavier Martinez Canillas * Routine: board_init 5577eea280SJavier Martinez Canillas * Description: Early hardware init. 5677eea280SJavier Martinez Canillas */ 5777eea280SJavier Martinez Canillas int board_init(void) 5877eea280SJavier Martinez Canillas { 5977eea280SJavier Martinez Canillas gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 6077eea280SJavier Martinez Canillas /* boot param addr */ 6177eea280SJavier Martinez Canillas gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 6277eea280SJavier Martinez Canillas 63f3b4bc45SEnric Balletbo i Serra #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 64f3b4bc45SEnric Balletbo i Serra status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); 65f3b4bc45SEnric Balletbo i Serra #endif 66f3b4bc45SEnric Balletbo i Serra 6777eea280SJavier Martinez Canillas return 0; 6877eea280SJavier Martinez Canillas } 6977eea280SJavier Martinez Canillas 7077eea280SJavier Martinez Canillas #ifdef CONFIG_SPL_BUILD 7177eea280SJavier Martinez Canillas /* 7277eea280SJavier Martinez Canillas * Routine: omap_rev_string 7377eea280SJavier Martinez Canillas * Description: For SPL builds output board rev 7477eea280SJavier Martinez Canillas */ 7577eea280SJavier Martinez Canillas void omap_rev_string(void) 7677eea280SJavier Martinez Canillas { 7777eea280SJavier Martinez Canillas } 7877eea280SJavier Martinez Canillas 7977eea280SJavier Martinez Canillas /* 8077eea280SJavier Martinez Canillas * Routine: get_board_mem_timings 8177eea280SJavier Martinez Canillas * Description: If we use SPL then there is no x-loader nor config header 8277eea280SJavier Martinez Canillas * so we have to setup the DDR timings ourself on both banks. 8377eea280SJavier Martinez Canillas */ 8477eea280SJavier Martinez Canillas void get_board_mem_timings(struct board_sdrc_timings *timings) 8577eea280SJavier Martinez Canillas { 8677eea280SJavier Martinez Canillas timings->mr = MICRON_V_MR_165; 8777eea280SJavier Martinez Canillas #ifdef CONFIG_BOOT_NAND 8877eea280SJavier Martinez Canillas timings->mcfg = MICRON_V_MCFG_200(256 << 20); 8977eea280SJavier Martinez Canillas timings->ctrla = MICRON_V_ACTIMA_200; 9077eea280SJavier Martinez Canillas timings->ctrlb = MICRON_V_ACTIMB_200; 9177eea280SJavier Martinez Canillas timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 9277eea280SJavier Martinez Canillas #else 9377eea280SJavier Martinez Canillas if (get_cpu_family() == CPU_OMAP34XX) { 9477eea280SJavier Martinez Canillas timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 9577eea280SJavier Martinez Canillas timings->ctrla = NUMONYX_V_ACTIMA_165; 9677eea280SJavier Martinez Canillas timings->ctrlb = NUMONYX_V_ACTIMB_165; 9777eea280SJavier Martinez Canillas timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 9877eea280SJavier Martinez Canillas 9977eea280SJavier Martinez Canillas } else { 10077eea280SJavier Martinez Canillas timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 10177eea280SJavier Martinez Canillas timings->ctrla = NUMONYX_V_ACTIMA_200; 10277eea280SJavier Martinez Canillas timings->ctrlb = NUMONYX_V_ACTIMB_200; 10377eea280SJavier Martinez Canillas timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 10477eea280SJavier Martinez Canillas } 10577eea280SJavier Martinez Canillas #endif 10677eea280SJavier Martinez Canillas } 10777eea280SJavier Martinez Canillas #endif 10877eea280SJavier Martinez Canillas 10977eea280SJavier Martinez Canillas #if defined(CONFIG_CMD_NET) 1106ed75ba7SLadislav Michl static void reset_net_chip(int gpio) 1116ed75ba7SLadislav Michl { 1126ed75ba7SLadislav Michl if (!gpio_request(gpio, "eth nrst")) { 1136ed75ba7SLadislav Michl gpio_direction_output(gpio, 1); 1146ed75ba7SLadislav Michl udelay(1); 1156ed75ba7SLadislav Michl gpio_set_value(gpio, 0); 1166ed75ba7SLadislav Michl udelay(40); 1176ed75ba7SLadislav Michl gpio_set_value(gpio, 1); 1186ed75ba7SLadislav Michl mdelay(10); 1196ed75ba7SLadislav Michl } 1206ed75ba7SLadislav Michl } 1216ed75ba7SLadislav Michl 12277eea280SJavier Martinez Canillas /* 12377eea280SJavier Martinez Canillas * Routine: setup_net_chip 12477eea280SJavier Martinez Canillas * Description: Setting up the configuration GPMC registers specific to the 12577eea280SJavier Martinez Canillas * Ethernet hardware. 12677eea280SJavier Martinez Canillas */ 12777eea280SJavier Martinez Canillas static void setup_net_chip(void) 12877eea280SJavier Martinez Canillas { 12977eea280SJavier Martinez Canillas struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 130*b0c47633SLadislav Michl static const u32 gpmc_lan_config[] = { 131*b0c47633SLadislav Michl NET_LAN9221_GPMC_CONFIG1, 132*b0c47633SLadislav Michl NET_LAN9221_GPMC_CONFIG2, 133*b0c47633SLadislav Michl NET_LAN9221_GPMC_CONFIG3, 134*b0c47633SLadislav Michl NET_LAN9221_GPMC_CONFIG4, 135*b0c47633SLadislav Michl NET_LAN9221_GPMC_CONFIG5, 136*b0c47633SLadislav Michl NET_LAN9221_GPMC_CONFIG6, 137*b0c47633SLadislav Michl }; 13877eea280SJavier Martinez Canillas 1396ed75ba7SLadislav Michl enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 1406ed75ba7SLadislav Michl CONFIG_SMC911X_BASE, GPMC_SIZE_16M); 14177eea280SJavier Martinez Canillas 14277eea280SJavier Martinez Canillas /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 14377eea280SJavier Martinez Canillas writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 14477eea280SJavier Martinez Canillas /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 14577eea280SJavier Martinez Canillas writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 14677eea280SJavier Martinez Canillas /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 14777eea280SJavier Martinez Canillas writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 14877eea280SJavier Martinez Canillas &ctrl_base->gpmc_nadv_ale); 14977eea280SJavier Martinez Canillas 1506ed75ba7SLadislav Michl reset_net_chip(64); 15177eea280SJavier Martinez Canillas } 152*b0c47633SLadislav Michl 153*b0c47633SLadislav Michl int board_eth_init(bd_t *bis) 154*b0c47633SLadislav Michl { 155*b0c47633SLadislav Michl #ifdef CONFIG_SMC911X 156*b0c47633SLadislav Michl return smc911x_initialize(0, CONFIG_SMC911X_BASE); 157*b0c47633SLadislav Michl #else 158*b0c47633SLadislav Michl return 0; 159*b0c47633SLadislav Michl #endif 160*b0c47633SLadislav Michl } 16177eea280SJavier Martinez Canillas #else 16277eea280SJavier Martinez Canillas static inline void setup_net_chip(void) {} 16377eea280SJavier Martinez Canillas #endif 16477eea280SJavier Martinez Canillas 16577eea280SJavier Martinez Canillas #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 16677eea280SJavier Martinez Canillas int board_mmc_init(bd_t *bis) 16777eea280SJavier Martinez Canillas { 168e3913f56SNikita Kiryanov return omap_mmc_init(0, 0, 0, -1, -1); 16977eea280SJavier Martinez Canillas } 17077eea280SJavier Martinez Canillas #endif 17177eea280SJavier Martinez Canillas 172aac5450eSPaul Kocialkowski #if defined(CONFIG_GENERIC_MMC) 173aac5450eSPaul Kocialkowski void board_mmc_power_init(void) 174aac5450eSPaul Kocialkowski { 175aac5450eSPaul Kocialkowski twl4030_power_mmc_init(0); 176aac5450eSPaul Kocialkowski } 177aac5450eSPaul Kocialkowski #endif 178aac5450eSPaul Kocialkowski 179a2fa28bcSJavier Martinez Canillas void set_fdt(void) 180a2fa28bcSJavier Martinez Canillas { 181a2fa28bcSJavier Martinez Canillas switch (gd->bd->bi_arch_number) { 182a2fa28bcSJavier Martinez Canillas case MACH_TYPE_IGEP0020: 18340372244SEnric Balletbò i Serra setenv("fdtfile", "omap3-igep0020.dtb"); 184a2fa28bcSJavier Martinez Canillas break; 185a2fa28bcSJavier Martinez Canillas case MACH_TYPE_IGEP0030: 18640372244SEnric Balletbò i Serra setenv("fdtfile", "omap3-igep0030.dtb"); 187a2fa28bcSJavier Martinez Canillas break; 188a2fa28bcSJavier Martinez Canillas } 189a2fa28bcSJavier Martinez Canillas } 190a2fa28bcSJavier Martinez Canillas 19177eea280SJavier Martinez Canillas /* 19277eea280SJavier Martinez Canillas * Routine: misc_init_r 19377eea280SJavier Martinez Canillas * Description: Configure board specific parts 19477eea280SJavier Martinez Canillas */ 19577eea280SJavier Martinez Canillas int misc_init_r(void) 19677eea280SJavier Martinez Canillas { 19777eea280SJavier Martinez Canillas twl4030_power_init(); 19877eea280SJavier Martinez Canillas 19977eea280SJavier Martinez Canillas setup_net_chip(); 20077eea280SJavier Martinez Canillas 201679f82c3SPaul Kocialkowski omap_die_id_display(); 20277eea280SJavier Martinez Canillas 203a2fa28bcSJavier Martinez Canillas set_fdt(); 204a2fa28bcSJavier Martinez Canillas 20577eea280SJavier Martinez Canillas return 0; 20677eea280SJavier Martinez Canillas } 20777eea280SJavier Martinez Canillas 20877eea280SJavier Martinez Canillas /* 20977eea280SJavier Martinez Canillas * Routine: set_muxconf_regs 21077eea280SJavier Martinez Canillas * Description: Setting up the configuration Mux registers specific to the 21177eea280SJavier Martinez Canillas * hardware. Many pins need to be moved from protect to primary 21277eea280SJavier Martinez Canillas * mode. 21377eea280SJavier Martinez Canillas */ 21477eea280SJavier Martinez Canillas void set_muxconf_regs(void) 21577eea280SJavier Martinez Canillas { 21677eea280SJavier Martinez Canillas MUX_DEFAULT(); 21777eea280SJavier Martinez Canillas 21877eea280SJavier Martinez Canillas #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 21977eea280SJavier Martinez Canillas MUX_IGEP0020(); 22077eea280SJavier Martinez Canillas #endif 22177eea280SJavier Martinez Canillas 22277eea280SJavier Martinez Canillas #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 22377eea280SJavier Martinez Canillas MUX_IGEP0030(); 22477eea280SJavier Martinez Canillas #endif 22577eea280SJavier Martinez Canillas } 226