177eea280SJavier Martinez Canillas /* 277eea280SJavier Martinez Canillas * (C) Copyright 2010 377eea280SJavier Martinez Canillas * ISEE 2007 SL, <www.iseebcn.com> 477eea280SJavier Martinez Canillas * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 677eea280SJavier Martinez Canillas */ 777eea280SJavier Martinez Canillas #include <common.h> 8b3f4ca11SSimon Glass #include <dm.h> 9b3f4ca11SSimon Glass #include <ns16550.h> 1077eea280SJavier Martinez Canillas #include <twl4030.h> 1177eea280SJavier Martinez Canillas #include <netdev.h> 1277eea280SJavier Martinez Canillas #include <asm/gpio.h> 1377eea280SJavier Martinez Canillas #include <asm/io.h> 1477eea280SJavier Martinez Canillas #include <asm/arch/mem.h> 1577eea280SJavier Martinez Canillas #include <asm/arch/mmc_host_def.h> 1677eea280SJavier Martinez Canillas #include <asm/arch/mux.h> 1777eea280SJavier Martinez Canillas #include <asm/arch/sys_proto.h> 1877eea280SJavier Martinez Canillas #include <asm/mach-types.h> 1977eea280SJavier Martinez Canillas #include "igep00x0.h" 2077eea280SJavier Martinez Canillas 2177eea280SJavier Martinez Canillas DECLARE_GLOBAL_DATA_PTR; 2277eea280SJavier Martinez Canillas 2377eea280SJavier Martinez Canillas #if defined(CONFIG_CMD_NET) 2477eea280SJavier Martinez Canillas /* GPMC definitions for LAN9221 chips */ 2577eea280SJavier Martinez Canillas static const u32 gpmc_lan_config[] = { 2677eea280SJavier Martinez Canillas NET_LAN9221_GPMC_CONFIG1, 2777eea280SJavier Martinez Canillas NET_LAN9221_GPMC_CONFIG2, 2877eea280SJavier Martinez Canillas NET_LAN9221_GPMC_CONFIG3, 2977eea280SJavier Martinez Canillas NET_LAN9221_GPMC_CONFIG4, 3077eea280SJavier Martinez Canillas NET_LAN9221_GPMC_CONFIG5, 3177eea280SJavier Martinez Canillas NET_LAN9221_GPMC_CONFIG6, 3277eea280SJavier Martinez Canillas }; 3377eea280SJavier Martinez Canillas #endif 3477eea280SJavier Martinez Canillas 35b3f4ca11SSimon Glass static const struct ns16550_platdata igep_serial = { 36b3f4ca11SSimon Glass OMAP34XX_UART3, 37b3f4ca11SSimon Glass 2, 38b3f4ca11SSimon Glass V_NS16550_CLK 39b3f4ca11SSimon Glass }; 40b3f4ca11SSimon Glass 41b3f4ca11SSimon Glass U_BOOT_DEVICE(igep_uart) = { 42b3f4ca11SSimon Glass "serial_omap", 43b3f4ca11SSimon Glass &igep_serial 44b3f4ca11SSimon Glass }; 45b3f4ca11SSimon Glass 4677eea280SJavier Martinez Canillas /* 4777eea280SJavier Martinez Canillas * Routine: board_init 4877eea280SJavier Martinez Canillas * Description: Early hardware init. 4977eea280SJavier Martinez Canillas */ 5077eea280SJavier Martinez Canillas int board_init(void) 5177eea280SJavier Martinez Canillas { 5277eea280SJavier Martinez Canillas gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 5377eea280SJavier Martinez Canillas /* boot param addr */ 5477eea280SJavier Martinez Canillas gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 5577eea280SJavier Martinez Canillas 5677eea280SJavier Martinez Canillas return 0; 5777eea280SJavier Martinez Canillas } 5877eea280SJavier Martinez Canillas 599d4f5421SJavier Martinez Canillas #if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) 609d4f5421SJavier Martinez Canillas void show_boot_progress(int val) 619d4f5421SJavier Martinez Canillas { 629d4f5421SJavier Martinez Canillas if (val < 0) { 639d4f5421SJavier Martinez Canillas /* something went wrong */ 649d4f5421SJavier Martinez Canillas return; 659d4f5421SJavier Martinez Canillas } 669d4f5421SJavier Martinez Canillas 679d4f5421SJavier Martinez Canillas if (!gpio_request(IGEP00X0_GPIO_LED, "")) 689d4f5421SJavier Martinez Canillas gpio_direction_output(IGEP00X0_GPIO_LED, 1); 699d4f5421SJavier Martinez Canillas } 709d4f5421SJavier Martinez Canillas #endif 719d4f5421SJavier Martinez Canillas 7277eea280SJavier Martinez Canillas #ifdef CONFIG_SPL_BUILD 7377eea280SJavier Martinez Canillas /* 7477eea280SJavier Martinez Canillas * Routine: omap_rev_string 7577eea280SJavier Martinez Canillas * Description: For SPL builds output board rev 7677eea280SJavier Martinez Canillas */ 7777eea280SJavier Martinez Canillas void omap_rev_string(void) 7877eea280SJavier Martinez Canillas { 7977eea280SJavier Martinez Canillas } 8077eea280SJavier Martinez Canillas 8177eea280SJavier Martinez Canillas /* 8277eea280SJavier Martinez Canillas * Routine: get_board_mem_timings 8377eea280SJavier Martinez Canillas * Description: If we use SPL then there is no x-loader nor config header 8477eea280SJavier Martinez Canillas * so we have to setup the DDR timings ourself on both banks. 8577eea280SJavier Martinez Canillas */ 8677eea280SJavier Martinez Canillas void get_board_mem_timings(struct board_sdrc_timings *timings) 8777eea280SJavier Martinez Canillas { 8877eea280SJavier Martinez Canillas timings->mr = MICRON_V_MR_165; 8977eea280SJavier Martinez Canillas #ifdef CONFIG_BOOT_NAND 9077eea280SJavier Martinez Canillas timings->mcfg = MICRON_V_MCFG_200(256 << 20); 9177eea280SJavier Martinez Canillas timings->ctrla = MICRON_V_ACTIMA_200; 9277eea280SJavier Martinez Canillas timings->ctrlb = MICRON_V_ACTIMB_200; 9377eea280SJavier Martinez Canillas timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 9477eea280SJavier Martinez Canillas #else 9577eea280SJavier Martinez Canillas if (get_cpu_family() == CPU_OMAP34XX) { 9677eea280SJavier Martinez Canillas timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); 9777eea280SJavier Martinez Canillas timings->ctrla = NUMONYX_V_ACTIMA_165; 9877eea280SJavier Martinez Canillas timings->ctrlb = NUMONYX_V_ACTIMB_165; 9977eea280SJavier Martinez Canillas timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 10077eea280SJavier Martinez Canillas 10177eea280SJavier Martinez Canillas } else { 10277eea280SJavier Martinez Canillas timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); 10377eea280SJavier Martinez Canillas timings->ctrla = NUMONYX_V_ACTIMA_200; 10477eea280SJavier Martinez Canillas timings->ctrlb = NUMONYX_V_ACTIMB_200; 10577eea280SJavier Martinez Canillas timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 10677eea280SJavier Martinez Canillas } 10777eea280SJavier Martinez Canillas #endif 10877eea280SJavier Martinez Canillas } 10977eea280SJavier Martinez Canillas #endif 11077eea280SJavier Martinez Canillas 11177eea280SJavier Martinez Canillas #if defined(CONFIG_CMD_NET) 11277eea280SJavier Martinez Canillas /* 11377eea280SJavier Martinez Canillas * Routine: setup_net_chip 11477eea280SJavier Martinez Canillas * Description: Setting up the configuration GPMC registers specific to the 11577eea280SJavier Martinez Canillas * Ethernet hardware. 11677eea280SJavier Martinez Canillas */ 11777eea280SJavier Martinez Canillas static void setup_net_chip(void) 11877eea280SJavier Martinez Canillas { 11977eea280SJavier Martinez Canillas struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 12077eea280SJavier Martinez Canillas 12177eea280SJavier Martinez Canillas enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 12277eea280SJavier Martinez Canillas GPMC_SIZE_16M); 12377eea280SJavier Martinez Canillas 12477eea280SJavier Martinez Canillas /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 12577eea280SJavier Martinez Canillas writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 12677eea280SJavier Martinez Canillas /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 12777eea280SJavier Martinez Canillas writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 12877eea280SJavier Martinez Canillas /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 12977eea280SJavier Martinez Canillas writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 13077eea280SJavier Martinez Canillas &ctrl_base->gpmc_nadv_ale); 13177eea280SJavier Martinez Canillas 13277eea280SJavier Martinez Canillas /* Make GPIO 64 as output pin and send a magic pulse through it */ 13377eea280SJavier Martinez Canillas if (!gpio_request(64, "")) { 13477eea280SJavier Martinez Canillas gpio_direction_output(64, 0); 13577eea280SJavier Martinez Canillas gpio_set_value(64, 1); 13677eea280SJavier Martinez Canillas udelay(1); 13777eea280SJavier Martinez Canillas gpio_set_value(64, 0); 13877eea280SJavier Martinez Canillas udelay(1); 13977eea280SJavier Martinez Canillas gpio_set_value(64, 1); 14077eea280SJavier Martinez Canillas } 14177eea280SJavier Martinez Canillas } 14277eea280SJavier Martinez Canillas #else 14377eea280SJavier Martinez Canillas static inline void setup_net_chip(void) {} 14477eea280SJavier Martinez Canillas #endif 14577eea280SJavier Martinez Canillas 14677eea280SJavier Martinez Canillas #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 14777eea280SJavier Martinez Canillas int board_mmc_init(bd_t *bis) 14877eea280SJavier Martinez Canillas { 149e3913f56SNikita Kiryanov return omap_mmc_init(0, 0, 0, -1, -1); 15077eea280SJavier Martinez Canillas } 15177eea280SJavier Martinez Canillas #endif 15277eea280SJavier Martinez Canillas 153*aac5450eSPaul Kocialkowski #if defined(CONFIG_GENERIC_MMC) 154*aac5450eSPaul Kocialkowski void board_mmc_power_init(void) 155*aac5450eSPaul Kocialkowski { 156*aac5450eSPaul Kocialkowski twl4030_power_mmc_init(0); 157*aac5450eSPaul Kocialkowski } 158*aac5450eSPaul Kocialkowski #endif 159*aac5450eSPaul Kocialkowski 160a2fa28bcSJavier Martinez Canillas void set_fdt(void) 161a2fa28bcSJavier Martinez Canillas { 162a2fa28bcSJavier Martinez Canillas switch (gd->bd->bi_arch_number) { 163a2fa28bcSJavier Martinez Canillas case MACH_TYPE_IGEP0020: 164a2fa28bcSJavier Martinez Canillas setenv("dtbfile", "omap3-igep0020.dtb"); 165a2fa28bcSJavier Martinez Canillas break; 166a2fa28bcSJavier Martinez Canillas case MACH_TYPE_IGEP0030: 167a2fa28bcSJavier Martinez Canillas setenv("dtbfile", "omap3-igep0030.dtb"); 168a2fa28bcSJavier Martinez Canillas break; 169a2fa28bcSJavier Martinez Canillas } 170a2fa28bcSJavier Martinez Canillas } 171a2fa28bcSJavier Martinez Canillas 17277eea280SJavier Martinez Canillas /* 17377eea280SJavier Martinez Canillas * Routine: misc_init_r 17477eea280SJavier Martinez Canillas * Description: Configure board specific parts 17577eea280SJavier Martinez Canillas */ 17677eea280SJavier Martinez Canillas int misc_init_r(void) 17777eea280SJavier Martinez Canillas { 17877eea280SJavier Martinez Canillas twl4030_power_init(); 17977eea280SJavier Martinez Canillas 18077eea280SJavier Martinez Canillas setup_net_chip(); 18177eea280SJavier Martinez Canillas 18277eea280SJavier Martinez Canillas dieid_num_r(); 18377eea280SJavier Martinez Canillas 184a2fa28bcSJavier Martinez Canillas set_fdt(); 185a2fa28bcSJavier Martinez Canillas 18677eea280SJavier Martinez Canillas return 0; 18777eea280SJavier Martinez Canillas } 18877eea280SJavier Martinez Canillas 18977eea280SJavier Martinez Canillas /* 19077eea280SJavier Martinez Canillas * Routine: set_muxconf_regs 19177eea280SJavier Martinez Canillas * Description: Setting up the configuration Mux registers specific to the 19277eea280SJavier Martinez Canillas * hardware. Many pins need to be moved from protect to primary 19377eea280SJavier Martinez Canillas * mode. 19477eea280SJavier Martinez Canillas */ 19577eea280SJavier Martinez Canillas void set_muxconf_regs(void) 19677eea280SJavier Martinez Canillas { 19777eea280SJavier Martinez Canillas MUX_DEFAULT(); 19877eea280SJavier Martinez Canillas 19977eea280SJavier Martinez Canillas #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) 20077eea280SJavier Martinez Canillas MUX_IGEP0020(); 20177eea280SJavier Martinez Canillas #endif 20277eea280SJavier Martinez Canillas 20377eea280SJavier Martinez Canillas #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) 20477eea280SJavier Martinez Canillas MUX_IGEP0030(); 20577eea280SJavier Martinez Canillas #endif 20677eea280SJavier Martinez Canillas } 20777eea280SJavier Martinez Canillas 20877eea280SJavier Martinez Canillas #if defined(CONFIG_CMD_NET) 20977eea280SJavier Martinez Canillas int board_eth_init(bd_t *bis) 21077eea280SJavier Martinez Canillas { 21177eea280SJavier Martinez Canillas int rc = 0; 21277eea280SJavier Martinez Canillas #ifdef CONFIG_SMC911X 21377eea280SJavier Martinez Canillas rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 21477eea280SJavier Martinez Canillas #endif 21577eea280SJavier Martinez Canillas return rc; 21677eea280SJavier Martinez Canillas } 21777eea280SJavier Martinez Canillas #endif 218