1 /* 2 * Altera SoCFPGA Clock and PLL configuration 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SOCFPGA_PLL_CONFIG_H__ 8 #define __SOCFPGA_PLL_CONFIG_H__ 9 10 #define CONFIG_HPS_DBCTRL_STAYOSC1 1 11 12 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 13 #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59 14 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 15 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 16 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 17 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 18 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 19 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 20 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 21 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 22 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 23 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 24 #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 25 #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 26 #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 27 #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 28 #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 29 30 #define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 31 #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 32 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 33 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 34 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 35 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 36 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 37 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 38 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39 39 #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 40 #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 41 #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 42 #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 43 #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 44 #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 45 #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 46 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 47 48 #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 49 #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 50 #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 51 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 52 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 54 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 55 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 56 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 57 #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 58 #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 59 60 #define CONFIG_HPS_CLK_OSC1_HZ 25000000 61 #define CONFIG_HPS_CLK_OSC2_HZ 25000000 62 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 63 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 64 #define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000 65 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 66 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 67 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 68 #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 69 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 70 #define CONFIG_HPS_CLK_NAND_HZ 488281 71 #define CONFIG_HPS_CLK_SDMMC_HZ 1953125 72 #define CONFIG_HPS_CLK_QSPI_HZ 375000000 73 #define CONFIG_HPS_CLK_SPIM_HZ 12500000 74 #define CONFIG_HPS_CLK_CAN0_HZ 12500000 75 #define CONFIG_HPS_CLK_CAN1_HZ 12500000 76 #define CONFIG_HPS_CLK_GPIODB_HZ 32000 77 #define CONFIG_HPS_CLK_L4_MP_HZ 100000000 78 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 79 80 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 81 #define CONFIG_HPS_ALTERAGRP_MAINCLK 4 82 #define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 83 84 85 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ 86