1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2009-2012 4 * Wojciech Dubowik <wojciech.dubowik@neratec.com> 5 * Luka Perkov <luka@openwrt.org> 6 */ 7 8 #include <common.h> 9 #include <miiphy.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 #include <asm/arch/mpp.h> 13 #include "iconnect.h" 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 int board_early_init_f(void) 18 { 19 /* 20 * default gpio configuration 21 * There are maximum 64 gpios controlled through 2 sets of registers 22 * the below configuration configures mainly initial LED status 23 */ 24 mvebu_config_gpio(ICONNECT_OE_VAL_LOW, 25 ICONNECT_OE_VAL_HIGH, 26 ICONNECT_OE_LOW, ICONNECT_OE_HIGH); 27 28 /* Multi-Purpose Pins Functionality configuration */ 29 static const u32 kwmpp_config[] = { 30 MPP0_NF_IO2, 31 MPP1_NF_IO3, 32 MPP2_NF_IO4, 33 MPP3_NF_IO5, 34 MPP4_NF_IO6, 35 MPP5_NF_IO7, 36 MPP6_SYSRST_OUTn, /* Reset signal */ 37 MPP7_GPO, 38 MPP8_TW_SDA, /* I2C */ 39 MPP9_TW_SCK, /* I2C */ 40 MPP10_UART0_TXD, 41 MPP11_UART0_RXD, 42 MPP12_GPO, /* Reset button */ 43 MPP13_SD_CMD, 44 MPP14_SD_D0, 45 MPP15_SD_D1, 46 MPP16_SD_D2, 47 MPP17_SD_D3, 48 MPP18_NF_IO0, 49 MPP19_NF_IO1, 50 MPP20_GE1_0, 51 MPP21_GE1_1, 52 MPP22_GE1_2, 53 MPP23_GE1_3, 54 MPP24_GE1_4, 55 MPP25_GE1_5, 56 MPP26_GE1_6, 57 MPP27_GE1_7, 58 MPP28_GPIO, 59 MPP29_GPIO, 60 MPP30_GE1_10, 61 MPP31_GE1_11, 62 MPP32_GE1_12, 63 MPP33_GE1_13, 64 MPP34_GE1_14, 65 MPP35_GPIO, /* OTB button */ 66 MPP36_AUDIO_SPDIFI, 67 MPP37_AUDIO_SPDIFO, 68 MPP38_GPIO, 69 MPP39_TDM_SPI_CS0, 70 MPP40_TDM_SPI_SCK, 71 MPP41_GPIO, /* LED brightness */ 72 MPP42_GPIO, /* LED power (blue) */ 73 MPP43_GPIO, /* LED power (red) */ 74 MPP44_GPIO, /* LED USB 1 */ 75 MPP45_GPIO, /* LED USB 2 */ 76 MPP46_GPIO, /* LED USB 3 */ 77 MPP47_GPIO, /* LED USB 4 */ 78 MPP48_GPIO, /* LED OTB */ 79 MPP49_GPIO, 80 0 81 }; 82 kirkwood_mpp_conf(kwmpp_config, NULL); 83 return 0; 84 } 85 86 int board_init(void) 87 { 88 /* adress of boot parameters */ 89 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 90 91 return 0; 92 } 93