1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * USB armory MkI board initialization 4 * http://inversepath.com/usbarmory 5 * 6 * Copyright (C) 2015, Inverse Path 7 * Andrej Rosano <andrej@inversepath.com> 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/arch/crm_regs.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/iomux-mx53.h> 17 #include <linux/errno.h> 18 #include <i2c.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <asm/gpio.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 u32 get_board_rev(void) 26 { 27 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; 28 struct fuse_bank *bank = &iim->bank[0]; 29 struct fuse_bank0_regs *fuse = 30 (struct fuse_bank0_regs *)bank->fuse_regs; 31 32 int rev = readl(&fuse->gp[6]); 33 34 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 35 } 36 37 struct fsl_esdhc_cfg esdhc_cfg[1] = { 38 {MMC_SDHC1_BASE_ADDR} 39 }; 40 41 int board_mmc_getcd(struct mmc *mmc) 42 { 43 /* CD not present */ 44 return 1; 45 } 46 47 int board_mmc_init(bd_t *bis) 48 { 49 int ret = 0; 50 51 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 52 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 53 54 return ret; 55 } 56 57 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 58 PAD_CTL_PUS_100K_UP) 59 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 60 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 61 #define PAD_CTRL_UP PAD_CTL_PUS_100K_UP 62 #define PAD_CTRL_GND PAD_CTL_PUS_100K_DOWN 63 64 static void setup_iomux_sd(void) 65 { 66 static const iomux_v3_cfg_t pads[] = { 67 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 68 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL), 69 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, 70 MX53_SDHC_PAD_CTRL), 71 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, 72 MX53_SDHC_PAD_CTRL), 73 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, 74 MX53_SDHC_PAD_CTRL), 75 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, 76 MX53_SDHC_PAD_CTRL), 77 MX53_PAD_EIM_DA13__GPIO3_13, 78 }; 79 80 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); 81 } 82 83 static void setup_iomux_led(void) 84 { 85 static const iomux_v3_cfg_t pads[] = { 86 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27, 87 PAD_CTL_PUS_100K_DOWN), 88 }; 89 90 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); 91 } 92 93 static void setup_iomux_i2c(void) 94 { 95 static const iomux_v3_cfg_t pads[] = { 96 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL), 97 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL), 98 }; 99 100 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); 101 } 102 103 static void setup_iomux_pinheader(void) 104 { 105 static const iomux_v3_cfg_t pads[] = { 106 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP), 107 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP), 108 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, 109 MX53_UART_PAD_CTRL), 110 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, 111 MX53_UART_PAD_CTRL), 112 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP), 113 }; 114 115 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); 116 } 117 118 static void setup_iomux_unused_boot(void) 119 { 120 static const iomux_v3_cfg_t pads[] = { 121 /* Pulled-up pads */ 122 NEW_PAD_CTRL(MX53_PAD_EIM_A21__GPIO2_17, PAD_CTRL_UP), 123 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__GPIO3_0, PAD_CTRL_UP), 124 125 /* Grounded pads */ 126 NEW_PAD_CTRL(MX53_PAD_EIM_LBA__GPIO2_27, PAD_CTRL_GND), 127 NEW_PAD_CTRL(MX53_PAD_EIM_EB0__GPIO2_28, PAD_CTRL_GND), 128 NEW_PAD_CTRL(MX53_PAD_EIM_EB1__GPIO2_29, PAD_CTRL_GND), 129 NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, PAD_CTRL_GND), 130 NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, PAD_CTRL_GND), 131 NEW_PAD_CTRL(MX53_PAD_EIM_A18__GPIO2_20, PAD_CTRL_GND), 132 NEW_PAD_CTRL(MX53_PAD_EIM_A19__GPIO2_19, PAD_CTRL_GND), 133 NEW_PAD_CTRL(MX53_PAD_EIM_A20__GPIO2_18, PAD_CTRL_GND), 134 NEW_PAD_CTRL(MX53_PAD_EIM_A22__GPIO2_16, PAD_CTRL_GND), 135 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__GPIO3_1, PAD_CTRL_GND), 136 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__GPIO3_2, PAD_CTRL_GND), 137 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__GPIO3_3, PAD_CTRL_GND), 138 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__GPIO3_4, PAD_CTRL_GND), 139 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__GPIO3_5, PAD_CTRL_GND), 140 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__GPIO3_6, PAD_CTRL_GND), 141 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__GPIO3_7, PAD_CTRL_GND), 142 NEW_PAD_CTRL(MX53_PAD_EIM_DA8__GPIO3_8, PAD_CTRL_GND), 143 NEW_PAD_CTRL(MX53_PAD_EIM_DA9__GPIO3_9, PAD_CTRL_GND), 144 NEW_PAD_CTRL(MX53_PAD_EIM_DA10__GPIO3_10, PAD_CTRL_GND), 145 }; 146 147 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); 148 } 149 150 static void setup_iomux_unused_nc(void) 151 { 152 /* Out of reset values define the pin values before the 153 ROM is executed so we force all the not connected pins 154 to a known state */ 155 static const iomux_v3_cfg_t pads[] = { 156 /* CONTROL PINS block */ 157 NEW_PAD_CTRL(MX53_PAD_GPIO_0__GPIO1_0, PAD_CTRL_UP), 158 NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, PAD_CTRL_UP), 159 NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTRL_UP), 160 NEW_PAD_CTRL(MX53_PAD_GPIO_3__GPIO1_3, PAD_CTRL_UP), 161 NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTRL_UP), 162 NEW_PAD_CTRL(MX53_PAD_GPIO_5__GPIO1_5, PAD_CTRL_UP), 163 NEW_PAD_CTRL(MX53_PAD_GPIO_6__GPIO1_6, PAD_CTRL_UP), 164 NEW_PAD_CTRL(MX53_PAD_GPIO_7__GPIO1_7, PAD_CTRL_UP), 165 NEW_PAD_CTRL(MX53_PAD_GPIO_8__GPIO1_8, PAD_CTRL_UP), 166 NEW_PAD_CTRL(MX53_PAD_GPIO_9__GPIO1_9, PAD_CTRL_UP), 167 NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTRL_UP), 168 NEW_PAD_CTRL(MX53_PAD_GPIO_11__GPIO4_1, PAD_CTRL_UP), 169 NEW_PAD_CTRL(MX53_PAD_GPIO_12__GPIO4_2, PAD_CTRL_UP), 170 NEW_PAD_CTRL(MX53_PAD_GPIO_13__GPIO4_3, PAD_CTRL_UP), 171 NEW_PAD_CTRL(MX53_PAD_GPIO_14__GPIO4_4, PAD_CTRL_UP), 172 NEW_PAD_CTRL(MX53_PAD_GPIO_16__GPIO7_11, PAD_CTRL_UP), 173 NEW_PAD_CTRL(MX53_PAD_GPIO_17__GPIO7_12, PAD_CTRL_UP), 174 NEW_PAD_CTRL(MX53_PAD_GPIO_18__GPIO7_13, PAD_CTRL_UP), 175 NEW_PAD_CTRL(MX53_PAD_GPIO_19__GPIO4_5, PAD_CTRL_UP), 176 177 /* EIM block */ 178 NEW_PAD_CTRL(MX53_PAD_EIM_OE__GPIO2_25, PAD_CTRL_UP), 179 NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__GPIO5_0, PAD_CTRL_UP), 180 /* EIM_LBA: setup_iomux_unused_boot() */ 181 NEW_PAD_CTRL(MX53_PAD_EIM_RW__GPIO2_26, PAD_CTRL_UP), 182 /* EIM_EB0: setup_iomux_unused_boot() */ 183 /* EIM_EB1: setup_iomux_unused_boot() */ 184 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__GPIO2_30, PAD_CTRL_UP), 185 NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, PAD_CTRL_UP), 186 NEW_PAD_CTRL(MX53_PAD_EIM_CS0__GPIO2_23, PAD_CTRL_UP), 187 NEW_PAD_CTRL(MX53_PAD_EIM_CS1__GPIO2_24, PAD_CTRL_UP), 188 /* EIM_A16: setup_iomux_unused_boot() */ 189 /* EIM_A17: setup_iomux_unused_boot() */ 190 /* EIM_A18: setup_iomux_unused_boot() */ 191 /* EIM_A19: setup_iomux_unused_boot() */ 192 /* EIM_A20: setup_iomux_unused_boot() */ 193 /* EIM_A21: setup_iomux_unused_boot() */ 194 /* EIM_A22: setup_iomux_unused_boot() */ 195 NEW_PAD_CTRL(MX53_PAD_EIM_A23__GPIO6_6, PAD_CTRL_UP), 196 NEW_PAD_CTRL(MX53_PAD_EIM_A24__GPIO5_4, PAD_CTRL_UP), 197 NEW_PAD_CTRL(MX53_PAD_EIM_A25__GPIO5_2, PAD_CTRL_UP), 198 NEW_PAD_CTRL(MX53_PAD_EIM_D16__GPIO3_16, PAD_CTRL_UP), 199 NEW_PAD_CTRL(MX53_PAD_EIM_D17__GPIO3_17, PAD_CTRL_UP), 200 NEW_PAD_CTRL(MX53_PAD_EIM_D18__GPIO3_18, PAD_CTRL_UP), 201 NEW_PAD_CTRL(MX53_PAD_EIM_D19__GPIO3_19, PAD_CTRL_UP), 202 NEW_PAD_CTRL(MX53_PAD_EIM_D20__GPIO3_20, PAD_CTRL_UP), 203 NEW_PAD_CTRL(MX53_PAD_EIM_D21__GPIO3_21, PAD_CTRL_UP), 204 NEW_PAD_CTRL(MX53_PAD_EIM_D22__GPIO3_22, PAD_CTRL_UP), 205 NEW_PAD_CTRL(MX53_PAD_EIM_D23__GPIO3_23, PAD_CTRL_UP), 206 NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, PAD_CTRL_UP), 207 NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, PAD_CTRL_UP), 208 NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, PAD_CTRL_UP), 209 NEW_PAD_CTRL(MX53_PAD_EIM_D27__GPIO3_27, PAD_CTRL_UP), 210 /* EIM_D28: setup_iomux_unused_boot() */ 211 /* EIM_D29: setup_iomux_unused_boot() */ 212 NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, PAD_CTRL_UP), 213 NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, PAD_CTRL_UP), 214 /* EIM_DA0: setup_iomux_unused_boot() */ 215 /* EIM_DA1: setup_iomux_unused_boot() */ 216 /* EIM_DA2: setup_iomux_unused_boot() */ 217 /* EIM_DA3: setup_iomux_unused_boot() */ 218 /* EIM_DA4: setup_iomux_unused_boot() */ 219 /* EIM_DA5: setup_iomux_unused_boot() */ 220 /* EIM_DA6: setup_iomux_unused_boot() */ 221 /* EIM_DA7: setup_iomux_unused_boot() */ 222 /* EIM_DA8: setup_iomux_unused_boot() */ 223 /* EIM_DA9: setup_iomux_unused_boot() */ 224 /* EIM_DA10: setup_iomux_unused_boot() */ 225 NEW_PAD_CTRL(MX53_PAD_EIM_DA11__GPIO3_11, PAD_CTRL_UP), 226 NEW_PAD_CTRL(MX53_PAD_EIM_DA12__GPIO3_12, PAD_CTRL_UP), 227 NEW_PAD_CTRL(MX53_PAD_EIM_DA13__GPIO3_13, PAD_CTRL_UP), 228 NEW_PAD_CTRL(MX53_PAD_EIM_DA14__GPIO3_14, PAD_CTRL_UP), 229 NEW_PAD_CTRL(MX53_PAD_EIM_DA15__GPIO3_15, PAD_CTRL_UP), 230 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__GPIO6_12, PAD_CTRL_UP), 231 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__GPIO6_13, PAD_CTRL_UP), 232 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__GPIO6_8, PAD_CTRL_UP), 233 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__GPIO6_7, PAD_CTRL_UP), 234 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__GPIO6_9, PAD_CTRL_UP), 235 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__GPIO6_10, PAD_CTRL_UP), 236 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__GPIO6_11, PAD_CTRL_UP), 237 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__GPIO6_14, PAD_CTRL_UP), 238 NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, PAD_CTRL_UP), 239 NEW_PAD_CTRL(MX53_PAD_NANDF_CS3__GPIO6_16, PAD_CTRL_UP), 240 241 /* MISC block */ 242 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__GPIO1_31, PAD_CTRL_UP), 243 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__GPIO1_22, PAD_CTRL_UP), 244 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__GPIO1_25, PAD_CTRL_UP), 245 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__GPIO1_23, PAD_CTRL_UP), 246 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__GPIO1_24, PAD_CTRL_UP), 247 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__GPIO1_28, PAD_CTRL_UP), 248 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__GPIO1_27, PAD_CTRL_UP), 249 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__GPIO1_26, PAD_CTRL_UP), 250 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__GPIO1_30, PAD_CTRL_UP), 251 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__GPIO1_29, PAD_CTRL_UP), 252 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__GPIO4_6, PAD_CTRL_UP), 253 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__GPIO4_7, PAD_CTRL_UP), 254 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__GPIO4_8, PAD_CTRL_UP), 255 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__GPIO4_9, PAD_CTRL_UP), 256 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__GPIO4_10, PAD_CTRL_UP), 257 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__GPIO4_11, PAD_CTRL_UP), 258 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__GPIO4_12, PAD_CTRL_UP), 259 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__GPIO4_13, PAD_CTRL_UP), 260 NEW_PAD_CTRL(MX53_PAD_KEY_COL4__GPIO4_14, PAD_CTRL_UP), 261 NEW_PAD_CTRL(MX53_PAD_KEY_ROW4__GPIO4_15, PAD_CTRL_UP), 262 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__GPIO1_11, PAD_CTRL_UP), 263 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__GPIO1_10, PAD_CTRL_UP), 264 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__GPIO1_15, PAD_CTRL_UP), 265 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__GPIO1_14, PAD_CTRL_UP), 266 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__GPIO1_13, PAD_CTRL_UP), 267 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__GPIO1_12, PAD_CTRL_UP), 268 NEW_PAD_CTRL(MX53_PAD_PATA_BUFFER_EN__GPIO7_1, PAD_CTRL_UP), 269 NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__GPIO7_9, PAD_CTRL_UP), 270 NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__GPIO7_10, PAD_CTRL_UP), 271 NEW_PAD_CTRL(MX53_PAD_PATA_DA_0__GPIO7_6, PAD_CTRL_UP), 272 NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__GPIO7_7, PAD_CTRL_UP), 273 NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__GPIO7_8, PAD_CTRL_UP), 274 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__GPIO2_0, PAD_CTRL_UP), 275 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__GPIO2_1, PAD_CTRL_UP), 276 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__GPIO2_2, PAD_CTRL_UP), 277 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__GPIO2_3, PAD_CTRL_UP), 278 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__GPIO2_4, PAD_CTRL_UP), 279 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__GPIO2_5, PAD_CTRL_UP), 280 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__GPIO2_6, PAD_CTRL_UP), 281 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__GPIO2_7, PAD_CTRL_UP), 282 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__GPIO2_8, PAD_CTRL_UP), 283 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__GPIO2_9, PAD_CTRL_UP), 284 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__GPIO2_10, PAD_CTRL_UP), 285 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__GPIO2_11, PAD_CTRL_UP), 286 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__GPIO2_12, PAD_CTRL_UP), 287 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__GPIO2_13, PAD_CTRL_UP), 288 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__GPIO2_14, PAD_CTRL_UP), 289 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__GPIO2_15, PAD_CTRL_UP), 290 NEW_PAD_CTRL(MX53_PAD_PATA_DIOR__GPIO7_3, PAD_CTRL_UP), 291 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__GPIO6_17, PAD_CTRL_UP), 292 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__GPIO6_18, PAD_CTRL_UP), 293 NEW_PAD_CTRL(MX53_PAD_PATA_DMARQ__GPIO7_0, PAD_CTRL_UP), 294 NEW_PAD_CTRL(MX53_PAD_PATA_INTRQ__GPIO7_2, PAD_CTRL_UP), 295 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__GPIO7_5, PAD_CTRL_UP), 296 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__GPIO7_4, PAD_CTRL_UP), 297 298 /* IPU block */ 299 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT4__GPIO5_22, PAD_CTRL_UP), 300 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT5__GPIO5_23, PAD_CTRL_UP), 301 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT6__GPIO5_24, PAD_CTRL_UP), 302 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT7__GPIO5_25, PAD_CTRL_UP), 303 /* CSI0_DAT8: setup_iomux_pinheader() */ 304 /* CSI0_DAT9: setup_iomux_pinheader() */ 305 /* CSI0_DAT10: setup_iomux_pinheader() */ 306 /* CSI0_DAT11: setup_iomux_pinheader() */ 307 /* CSI0_DAT12: setup_iomux_pinheader() */ 308 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__GPIO5_31, PAD_CTRL_UP), 309 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT14__GPIO6_0, PAD_CTRL_UP), 310 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT15__GPIO6_1, PAD_CTRL_UP), 311 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT16__GPIO6_2, PAD_CTRL_UP), 312 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT17__GPIO6_3, PAD_CTRL_UP), 313 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT18__GPIO6_4, PAD_CTRL_UP), 314 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT19__GPIO6_5, PAD_CTRL_UP), 315 NEW_PAD_CTRL(MX53_PAD_CSI0_VSYNC__GPIO5_21, PAD_CTRL_UP), 316 NEW_PAD_CTRL(MX53_PAD_CSI0_PIXCLK__GPIO5_18, PAD_CTRL_UP), 317 NEW_PAD_CTRL(MX53_PAD_CSI0_MCLK__GPIO5_19, PAD_CTRL_UP), 318 NEW_PAD_CTRL(MX53_PAD_CSI0_DATA_EN__GPIO5_20, PAD_CTRL_UP), 319 NEW_PAD_CTRL(MX53_PAD_DI0_PIN2__GPIO4_18, PAD_CTRL_UP), 320 NEW_PAD_CTRL(MX53_PAD_DI0_PIN3__GPIO4_19, PAD_CTRL_UP), 321 NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, PAD_CTRL_UP), 322 NEW_PAD_CTRL(MX53_PAD_DI0_PIN15__GPIO4_17, PAD_CTRL_UP), 323 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT0__GPIO4_21, PAD_CTRL_UP), 324 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT1__GPIO4_22, PAD_CTRL_UP), 325 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT2__GPIO4_23, PAD_CTRL_UP), 326 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT3__GPIO4_24, PAD_CTRL_UP), 327 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT4__GPIO4_25, PAD_CTRL_UP), 328 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT5__GPIO4_26, PAD_CTRL_UP), 329 /* DISP0_DAT6: setup_iomux_led() */ 330 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT7__GPIO4_28, PAD_CTRL_UP), 331 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT8__GPIO4_29, PAD_CTRL_UP), 332 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT9__GPIO4_30, PAD_CTRL_UP), 333 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT10__GPIO4_31, PAD_CTRL_UP), 334 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT11__GPIO5_5, PAD_CTRL_UP), 335 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT12__GPIO5_6, PAD_CTRL_UP), 336 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT13__GPIO5_7, PAD_CTRL_UP), 337 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT14__GPIO5_8, PAD_CTRL_UP), 338 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT15__GPIO5_9, PAD_CTRL_UP), 339 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT16__GPIO5_10, PAD_CTRL_UP), 340 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT17__GPIO5_11, PAD_CTRL_UP), 341 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT18__GPIO5_12, PAD_CTRL_UP), 342 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT19__GPIO5_13, PAD_CTRL_UP), 343 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT20__GPIO5_14, PAD_CTRL_UP), 344 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT21__GPIO5_15, PAD_CTRL_UP), 345 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT22__GPIO5_16, PAD_CTRL_UP), 346 NEW_PAD_CTRL(MX53_PAD_DISP0_DAT23__GPIO5_17, PAD_CTRL_UP), 347 NEW_PAD_CTRL(MX53_PAD_DI0_DISP_CLK__GPIO4_16, PAD_CTRL_UP), 348 349 /* LVDS block */ 350 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX0_P__GPIO7_30, PAD_CTRL_UP), 351 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX1_P__GPIO7_28, PAD_CTRL_UP), 352 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX2_P__GPIO7_26, PAD_CTRL_UP), 353 NEW_PAD_CTRL(MX53_PAD_LVDS0_TX3_P__GPIO7_22, PAD_CTRL_UP), 354 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX0_P__GPIO6_30, PAD_CTRL_UP), 355 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX1_P__GPIO6_28, PAD_CTRL_UP), 356 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX2_P__GPIO6_24, PAD_CTRL_UP), 357 NEW_PAD_CTRL(MX53_PAD_LVDS1_TX3_P__GPIO6_22, PAD_CTRL_UP), 358 NEW_PAD_CTRL(MX53_PAD_LVDS0_CLK_P__GPIO7_24, PAD_CTRL_UP), 359 NEW_PAD_CTRL(MX53_PAD_LVDS1_CLK_P__GPIO6_26, PAD_CTRL_UP), 360 }; 361 362 imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); 363 } 364 365 #define CPU_CLOCK 800 366 367 static void set_clock(void) 368 { 369 u32 ref_clk = MXC_HCLK; 370 const uint32_t cpuclk = CPU_CLOCK; 371 const uint32_t dramclk = 400; 372 int ret; 373 374 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); 375 if (ret) 376 printf("CPU: Switch CPU clock to %dMHZ failed\n", cpuclk); 377 378 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); 379 if (ret) 380 printf("CPU: Switch peripheral clock to %dMHz failed\n", 381 dramclk); 382 383 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); 384 if (ret) 385 printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); 386 } 387 388 int board_early_init_f(void) 389 { 390 setup_iomux_unused_nc(); 391 setup_iomux_unused_boot(); 392 setup_iomux_sd(); 393 setup_iomux_led(); 394 setup_iomux_pinheader(); 395 set_clock(); 396 return 0; 397 } 398 399 int board_init(void) 400 { 401 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 402 setup_iomux_i2c(); 403 return 0; 404 } 405 406 int dram_init(void) 407 { 408 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30); 409 return 0; 410 } 411 412 int checkboard(void) 413 { 414 puts("Board: Inverse Path USB armory MkI\n"); 415 return 0; 416 } 417 418 #ifndef CONFIG_CMDLINE 419 static char *ext2_argv[] = { 420 "ext2load", 421 "mmc", 422 "0:1", 423 USBARMORY_FIT_ADDR, 424 USBARMORY_FIT_PATH 425 }; 426 427 static char *bootm_argv[] = { 428 "bootm", 429 USBARMORY_FIT_ADDR 430 }; 431 432 int board_run_command(const char *cmdline) 433 { 434 printf("%s %s %s %s %s\n", ext2_argv[0], ext2_argv[1], ext2_argv[2], 435 ext2_argv[3], ext2_argv[4]); 436 437 if (do_ext2load(NULL, 0, 5, ext2_argv) != 0) { 438 udelay(5*1000*1000); 439 return 1; 440 } 441 442 printf("%s %s\n", bootm_argv[0], bootm_argv[1]); 443 do_bootm(NULL, 0, 2, bootm_argv); 444 445 return 1; 446 } 447 #endif 448