1 /* 2 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/gpio.h> 9 #include <asm/fsp/fsp_support.h> 10 11 static const struct gpio_family gpio_family[] = { 12 GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0, 13 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST), 14 15 /* end of the table */ 16 GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0, 17 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR), 18 }; 19 20 static const struct gpio_pad gpio_pad[] = { 21 GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA, 22 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 23 NA, 29, NA, 0x4c38, NORTH), 24 GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA, 25 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 26 NA, 27, NA, 0x4c28, NORTH), 27 GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA, 28 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 29 NA, 20, NA, 0x4858, NORTH), 30 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW, 31 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 32 NA, 37, NA, 0x5018, NORTH), 33 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW, 34 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 35 NA, 42, NA, 0x5040, NORTH), 36 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW, 37 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 38 NA, 35, NA, 0x5008, NORTH), 39 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW, 40 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 41 NA, 40, NA, 0x5030, NORTH), 42 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW, 43 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 44 NA, 45, NA, 0x5058, NORTH), 45 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW, 46 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 47 NA, 34, NA, 0x5000, NORTH), 48 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW, 49 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 50 NA, 38, NA, 0x5020, NORTH), 51 GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW, 52 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 53 NA, 43, NA, 0x5048, NORTH), 54 GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW, 55 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 56 NA, 36, NA, 0x5010, NORTH), 57 GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW, 58 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 59 NA, 41, NA, 0x5038, NORTH), 60 GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW, 61 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 62 NA, 39, NA, 0x5028, NORTH), 63 GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW, 64 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 65 NA, 44, NA, 0x5050, NORTH), 66 GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA, 67 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 68 NA, 0, NA, 0x4400, NORTH), 69 GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA, 70 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 71 NA, 3, NA, 0x4418, NORTH), 72 GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA, 73 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 74 NA, 2, NA, 0x4438, NORTH), 75 GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA, 76 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, 77 NA, 1, NA, 0x4408, NORTH), 78 GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA, 79 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 80 NA, 5, NA, 0x4428, NORTH), 81 GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA, 82 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 83 NA, 4, NA, 0x4420, NORTH), 84 GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA, 85 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 86 NA, 8, NA, 0x4440, NORTH), 87 GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA, 88 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 89 NA, 2, NA, 0x4410, NORTH), 90 GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA, 91 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 92 NA, 9 , NA, 0x4800, NORTH), 93 GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA, 94 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 95 NA, 13, NA, 0x4820, NORTH), 96 GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA, 97 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 98 NA, 18, NA, 0x4848, NORTH), 99 GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA, 100 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 101 NA, 11, NA, 0x4810, NORTH), 102 GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA, 103 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 104 NA, 16, NA, 0x4838, NORTH), 105 GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA, 106 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 107 NA, 14, NA, 0x4828, NORTH), 108 GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA, 109 TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE, 110 EN_EDGE_RX_DATA, NO_INVERSION, 111 NA, 19, SCI, 0x4850, NORTH), 112 GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA, 113 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 114 NA, 12, SMI, 0x4818, NORTH), 115 GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA, 116 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 117 NA, 57, NA, 0x5458, NORTH), 118 GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA, 119 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 120 NA, 52, NA, 0x5430, NORTH), 121 GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA, 122 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, 123 NA, 47, NA, 0x5408, NORTH), 124 GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA, 125 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, 126 NA, 50, NA, 0x5420, NORTH), 127 GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA, 128 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 129 NA, 53, NA, 0x5438, NORTH), 130 GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA, 131 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 132 NA, 48, NA, 0x5410, NORTH), 133 GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA, 134 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, 135 NA, 54, NA, 0x5440, NORTH), 136 GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA, 137 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 138 NA, 51, NA, 0x5428, NORTH), 139 GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA, 140 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 141 NA, 46, NA, 0x5400, NORTH), 142 GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA, 143 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 144 NA, 58, NA, 0x5460, NORTH), 145 GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA, 146 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 147 NA, 49, NA, 0x5418, NORTH), 148 GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA, 149 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 150 NA, 56, NA, 0x5450, NORTH), 151 GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA, 152 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 153 NA, 55, NA, 0x5448, NORTH), 154 GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA, 155 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 156 NA, 24, NA, 0x4c10, NORTH), 157 GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA, 158 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 159 NA, 10, NA, 0x4808, NORTH), 160 GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA, 161 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 162 NA, 15, NA, 0x4830, NORTH), 163 GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA, 164 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 165 NA, 17, NA, 0x4840, NORTH), 166 GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA, 167 TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE, 168 EN_RX_DATA, INV_RX_DATA, 169 NA, 21, SCI, 0x4860, NORTH), 170 GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA, 171 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 172 NA, 23, NA, 0x4c08, NORTH), 173 GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA, 174 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 175 NA, 33, NA, 0x4c58, NORTH), 176 GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA, 177 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 178 NA, 31, NA, 0x4c48, NORTH), 179 GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA, 180 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 181 NA, 28, NA, 0x4c30, NORTH), 182 GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA, 183 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 184 NA, 26, NA, 0x4c20, NORTH), 185 GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA, 186 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 187 NA, 22, NA, 0x4c00, NORTH), 188 189 GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA, 190 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 191 NA, 18, NA, 0x4830, EAST), 192 GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA, 193 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 194 NA, 15, NA, 0x4818, EAST), 195 GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA, 196 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 197 NA, 21, NA, 0x4848, EAST), 198 GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA, 199 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 200 NA, 12, NA, 0x4800, EAST), 201 GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA, 202 NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION, 203 NA, 19, NA, 0x4838, EAST), 204 GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA, 205 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 206 NA, 16, NA, 0x4820, EAST), 207 GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA, 208 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 209 NA, 22, NA, 0x4850, EAST), 210 GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA, 211 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 212 NA, 13, NA, 0x4808, EAST), 213 GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA, 214 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 215 NA, 20, NA, 0x4840, EAST), 216 GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA, 217 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 218 NA, 17, NA, 0x4828, EAST), 219 GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA, 220 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 221 NA, 23, NA, 0x4858, EAST), 222 GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA, 223 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 224 NA, 14, NA, 0x4810, EAST), 225 GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA, 226 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 227 NA, 4, NA, 0x4420, EAST), 228 GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA, 229 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 230 NA, 1, NA, 0x4408, EAST), 231 GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA, 232 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 233 NA, 5, NA, 0x4428, EAST), 234 GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA, 235 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 236 NA, 7, NA, 0x4438, EAST), 237 GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA, 238 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 239 NA, 3, NA, 0x4418, EAST), 240 GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA, 241 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 242 NA, 0, NA, 0x4400, EAST), 243 GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA, 244 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 245 NA, 9, NA, 0x4448, EAST), 246 GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA, 247 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 248 NA, 6, NA, 0x4430, EAST), 249 GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA, 250 NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION, 251 NA, 10, NA, 0x4450, EAST), 252 GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA, 253 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 254 NA, 11, NA, 0x4458, EAST), 255 GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA, 256 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 257 NA, 2, NA, 0x4410, EAST), 258 259 GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH, 260 NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION, 261 NA, 9, NA, 0x4808, SOUTHEAST), 262 GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH, 263 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 264 NA, 16, NA, 0x4840, SOUTHEAST), 265 GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH, 266 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 267 NA, 10, NA, 0x4810, SOUTHEAST), 268 GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH, 269 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 270 NA, 17, NA, 0x4848, SOUTHEAST), 271 GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH, 272 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 273 NA, 13, NA, 0x4828, SOUTHEAST), 274 GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH, 275 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 276 NA, 19, NA, 0x4858, SOUTHEAST), 277 GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH, 278 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 279 NA, 41, NA, 0x5438, SOUTHEAST), 280 GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH, 281 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 282 NA, 39, NA, 0x5428, SOUTHEAST), 283 GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH, 284 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 285 NA, 37, NA, 0x5418, SOUTHEAST), 286 GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH, 287 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 288 NA, 42, NA, 0x5440, SOUTHEAST), 289 GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA, 290 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 291 NA, 43, NA, 0x5448, SOUTHEAST), 292 GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA, 293 TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE, 294 EN_RX_DATA, INV_RX_DATA, 295 NA, 46, NA, 0x5810, SOUTHEAST), 296 GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA, 297 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 298 NA, 48, NA, 0x5820, SOUTHEAST), 299 GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA, 300 NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION, 301 NA, 32, NA, 0x5030, SOUTHEAST), 302 GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA, 303 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 304 NA, 30, NA, 0x5020, SOUTHEAST), 305 GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA, 306 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 307 NA, 28, NA, 0x5010, SOUTHEAST), 308 GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA, 309 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 310 NA, 33, NA, 0x5038, SOUTHEAST), 311 GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA, 312 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 313 NA, 26, NA, 0x5000, SOUTHEAST), 314 GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA, 315 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 316 NA, 31, NA, 0x5028, SOUTHEAST), 317 GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA, 318 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 319 NA, 27, NA, 0x5008, SOUTHEAST), 320 GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA, 321 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 322 NA, 29, NA, 0x5018, SOUTHEAST), 323 GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA, 324 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 325 NA, 0, NA, 0x4400, SOUTHEAST), 326 GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA, 327 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 328 NA, 1, NA, 0x4410, SOUTHEAST), 329 GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA, 330 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 331 NA, 7, NA, 0x4438, SOUTHEAST), 332 GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA, 333 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 334 NA, 4, NA, 0x4420, SOUTHEAST), 335 GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA, 336 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 337 NA, 3, NA, 0x4418, SOUTHEAST), 338 GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA, 339 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 340 NA, 6, NA, 0x4430, SOUTHEAST), 341 GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA, 342 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 343 NA, 52, NA, 0x5840, SOUTHEAST), 344 GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA, 345 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 346 NA, 5, NA, 0x4428, SOUTHEAST), 347 GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA, 348 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 349 NA, 1, NA, 0x4408, SOUTHEAST), 350 GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA, 351 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 352 NA, 54, NA, 0x5850, SOUTHEAST), 353 GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA, 354 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 355 NA, 50, NA, 0x5830, SOUTHEAST), 356 GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA, 357 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 358 NA, 21, NA, 0x4c08, SOUTHEAST), 359 GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA, 360 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 361 NA, 24, NA, 0x4c20, SOUTHEAST), 362 GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA, 363 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 364 NA, 25, NA, 0x4c28, SOUTHEAST), 365 GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA, 366 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 367 NA, 20, NA, 0x4c00, SOUTHEAST), 368 GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA, 369 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 370 NA, 23, NA, 0x4c18, SOUTHEAST), 371 GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA, 372 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 373 NA, 22, NA, 0x4c10, SOUTHEAST), 374 GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA, 375 NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION, 376 NA, 47, NA, 0x5818, SOUTHEAST), 377 GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA, 378 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 379 NA, 12, NA, 0x4820, SOUTHEAST), 380 GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA, 381 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 382 NA, 15, NA, 0x4838, SOUTHEAST), 383 GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA, 384 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 385 NA, 18, NA, 0x4850, SOUTHEAST), 386 GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA, 387 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 388 NA, 11, NA, 0x4818, SOUTHEAST), 389 GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA, 390 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 391 NA, 14, NA, 0x4830, SOUTHEAST), 392 GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA, 393 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 394 NA, 8, NA, 0x4800, SOUTHEAST), 395 GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA, 396 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 397 NA, 36, NA, 0x5410, SOUTHEAST), 398 GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA, 399 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 400 NA, 35, NA, 0x5408, SOUTHEAST), 401 GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA, 402 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 403 NA, 40, NA, 0x5430, SOUTHEAST), 404 GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA, 405 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 406 NA, 34, NA, 0x5400, SOUTHEAST), 407 GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA, 408 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 409 NA, 38, NA, 0x5420, SOUTHEAST), 410 GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA, 411 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 412 NA, 49, NA, 0x5828, SOUTHEAST), 413 GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA, 414 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 415 NA, 44, NA, 0x5800, SOUTHEAST), 416 GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA, 417 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 418 NA, 2, NA, 0x4410, SOUTHWEST), 419 GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA, 420 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 421 NA, 6, NA, 0x4430, SOUTHWEST), 422 GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA, 423 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 424 NA, 4, NA, 0x4420, SOUTHWEST), 425 GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA, 426 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 427 NA, 7, NA, 0x4438, SOUTHWEST), 428 GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA, 429 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 430 NA, 1, NA, 0x4408, SOUTHWEST), 431 GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA, 432 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 433 NA, 5, NA, 0x4428, SOUTHWEST), 434 GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA, 435 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 436 NA, 0, NA, 0x4400, SOUTHWEST), 437 GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA, 438 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 439 NA, 3, NA, 0x4418, SOUTHWEST), 440 GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA, 441 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 442 NA, 16, NA, 0x4c00, SOUTHWEST), 443 GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA, 444 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 445 NA, 23, NA, 0x4c38, SOUTHWEST), 446 GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA, 447 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 448 NA, 20, NA, 0x4c20, SOUTHWEST), 449 GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA, 450 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 451 NA, 17, NA, 0x4c08, SOUTHWEST), 452 GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA, 453 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 454 NA, 18, NA, 0x4c10, SOUTHWEST), 455 GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA, 456 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 457 NA, 22, NA, 0x4c30, SOUTHWEST), 458 GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA, 459 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 460 NA, 19, NA, 0x4c18, SOUTHWEST), 461 GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA, 462 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 463 NA, 21, NA, 0x4c28, SOUTHWEST), 464 GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA, 465 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 466 NA, 11, NA, 0x4818, SOUTHWEST), 467 GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA, 468 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 469 NA, 8, NA, 0x4800, SOUTHWEST), 470 GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA, 471 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 472 NA, 9, NA, 0x4808, SOUTHWEST), 473 GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA, 474 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 475 NA, 13, NA, 0x4828, SOUTHWEST), 476 GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA, 477 NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION, 478 NA, 15, NA, 0x4838, SOUTHWEST), 479 GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA, 480 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 481 NA, 12, NA, 0x4820, SOUTHWEST), 482 GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA, 483 NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION, 484 NA, 10, NA, 0x4810, SOUTHWEST), 485 GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA, 486 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 487 NA, 14, NA, 0x4830, SOUTHWEST), 488 GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA, 489 NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION, 490 NA, 29, NA, 0x5028, SOUTHWEST), 491 GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA, 492 NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION, 493 NA, 25, NA, 0x5008, SOUTHWEST), 494 GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA, 495 NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE, 496 NA, 28, NA, 0x5020, SOUTHWEST), 497 GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA, 498 NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE, 499 NA, 31, NA, 0x5038, SOUTHWEST), 500 GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA, 501 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 502 NA, 50, NA, 0x5c10, SOUTHWEST), 503 GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA, 504 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 505 NA, 54, NA, 0x5c30, SOUTHWEST), 506 GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA, 507 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 508 NA, 52, NA, 0x5c20, SOUTHWEST), 509 GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA, 510 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE, 511 NA, 55, NA, 0x5C38, SOUTHWEST), 512 GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA, 513 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 514 NA, 48, NA, 0x5c00, SOUTHWEST), 515 GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA, 516 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 517 NA, 49, NA, 0x5c08, SOUTHWEST), 518 GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA, 519 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 520 NA, 51, NA, 0x5c18, SOUTHWEST), 521 GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA, 522 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 523 NA, 53, NA, 0x5c28, SOUTHWEST), 524 GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, 525 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 526 NA, 40, NA, 0x5800, SOUTHWEST), 527 GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, 528 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 529 NA, 41, NA, 0x5808, SOUTHWEST), 530 GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA, 531 NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION, 532 NA, 43, NA, 0x5818, SOUTHWEST), 533 GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA, 534 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 535 NA, 45, NA, 0x5828, SOUTHWEST), 536 GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA, 537 NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION, 538 NA, 42, NA, 0x5810, SOUTHWEST), 539 GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA, 540 NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 541 NA, 44, NA, 0x5820, SOUTHWEST), 542 GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA, 543 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 544 NA, 46, NA, 0x5830, SOUTHWEST), 545 GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA, 546 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION, 547 NA, 47, NA, 0x5838, SOUTHWEST), 548 GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA, 549 NA, NA, NA, NA, NA, NA, NA, NA, 550 NA, 48, NA, 0x5c00, SOUTHWEST), 551 GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA, 552 NA, NA, NA, NA, NA, NA, NA, NA, 553 NA, 49, NA, 0x5c08, SOUTHWEST), 554 GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA, 555 NA, NA, NA, NA, NA, NA, NA, NA, 556 NA, 51, NA, 0x5c18, SOUTHWEST), 557 GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA, 558 NA, NA, NA, NA, NA, NA, NA, NA, 559 NA, 53, NA, 0x5c28, SOUTHWEST), 560 GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA, 561 NA, NA, NA, NA, NA, NA, NA, 562 NA, 40, NA, 0x5800, SOUTHWEST), 563 GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA, 564 NA, NA, NA, NA, NA, NA, NA, 565 NA, 41, NA, 0x5808, SOUTHWEST), 566 GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA, 567 NA, NA, NA, ENABLE, NA, NA, NA, NA, 568 NA, 43, NA, 0x5818, SOUTHWEST), 569 GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA, 570 NA, NA, NA, NA, NA, NA, NA, NA, 571 NA, 45, NA, 0x5828, SOUTHWEST), 572 GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA, 573 NA, NA, NA, ENABLE, NA, NA, NA, NA, 574 NA, 42, NA, 0x5810, SOUTHWEST), 575 GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA, 576 NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA, 577 NA, 44, NA, 0x5820, SOUTHWEST), 578 GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA, 579 NA, NA, P_20K_H, NA, NA, NA, NA, NA, 580 NA, 46, NA, 0x5830, SOUTHWEST), 581 GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA, 582 NA, NA, P_20K_H, NA, NA, NA, NA, NA, 583 NA, 47, NA, 0x5838, SOUTHWEST), 584 585 /* end of the table */ 586 GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA, 587 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION, 588 NA, 0, NA, 0, TERMINATOR), 589 }; 590 591 void update_fsp_gpio_configs(const struct gpio_family **family, 592 const struct gpio_pad **pad) 593 { 594 *family = gpio_family; 595 *pad = gpio_pad; 596 } 597