xref: /openbmc/u-boot/board/imgtec/xilfpga/README (revision c66f5620)
1/*
2 * Copyright (C) 2016, Imagination Technologies Ltd.
3 *
4 * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com
5 */
6
7MIPSfpga
8=======================================
9
10MIPSfpga is an FPGA based development platform by Imagination Technologies
11As we are dealing with a MIPS core instantiated on an FPGA, specifications
12are fluid and can be varied in RTL.
13
14The example project provided by IMGTEC runs on the Nexys4DDR board by
15Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
16the example project and the Nexys4DDR board:
17
18- microAptiv UP core m14Kc
19- 50MHz clock speed
20- 128Mbyte DDR RAM	at 0x0000_0000
21- 8Kbyte RAM		at 0x1000_0000
22- axi_intc		at 0x1020_0000
23- axi_uart16550		at 0x1040_0000
24- axi_gpio		at 0x1060_0000
25- axi_i2c		at 0x10A0_0000
26- custom_gpio		at 0x10C0_0000
27- axi_ethernetlite	at 0x10E0_0000
28- 8Kbyte BootRAM	at 0x1FC0_0000
29- 16Mbyte QPI		at 0x1D00_0000
30
31Boot protocol:
32--------------
33
34The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
35This is for easy reprogrammibility via JTAG.
36
37DDR initialization is already handled by a HW IP block.
38
39When the example project bitstream is loaded, the cpu_reset button
40needs to be pressed.
41
42The bootram initializes the cache and axi_uart
43Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
44
45If there is, then that is considered as u-boot. u-boot is copied from
460x1D40_0000 to memory and the bootram jumps into u-boot code.
47
48At this point, the board is ready to load the Linux kernel + buildroot initramfs
49
50This can be done in multiple ways:
51
521- JTAG load the binary and jump into it.
532- Load kernel stored in the QSPI flash at 0x1D80_0000
543- Load uImage via tftp. Ethernet works in u-boot.
55   e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
56