1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * Copyright (C) 2013 Imagination Technologies 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <ide.h> 10 #include <netdev.h> 11 #include <pci.h> 12 #include <pci_gt64120.h> 13 #include <pci_msc01.h> 14 #include <rtc.h> 15 #include <serial.h> 16 17 #include <asm/addrspace.h> 18 #include <asm/io.h> 19 #include <asm/malta.h> 20 21 #include "superio.h" 22 23 enum core_card { 24 CORE_UNKNOWN, 25 CORE_LV, 26 CORE_FPGA6, 27 }; 28 29 enum sys_con { 30 SYSCON_UNKNOWN, 31 SYSCON_GT64120, 32 SYSCON_MSC01, 33 }; 34 35 static void malta_lcd_puts(const char *str) 36 { 37 int i; 38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); 39 40 /* print up to 8 characters of the string */ 41 for (i = 0; i < min((int)strlen(str), 8); i++) { 42 __raw_writel(str[i], reg); 43 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 44 } 45 46 /* fill the rest of the display with spaces */ 47 for (; i < 8; i++) { 48 __raw_writel(' ', reg); 49 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 50 } 51 } 52 53 static enum core_card malta_core_card(void) 54 { 55 u32 corid, rev; 56 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); 57 58 rev = __raw_readl(reg); 59 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; 60 61 switch (corid) { 62 case MALTA_REVISION_CORID_CORE_LV: 63 return CORE_LV; 64 65 case MALTA_REVISION_CORID_CORE_FPGA6: 66 return CORE_FPGA6; 67 68 default: 69 return CORE_UNKNOWN; 70 } 71 } 72 73 static enum sys_con malta_sys_con(void) 74 { 75 switch (malta_core_card()) { 76 case CORE_LV: 77 return SYSCON_GT64120; 78 79 case CORE_FPGA6: 80 return SYSCON_MSC01; 81 82 default: 83 return SYSCON_UNKNOWN; 84 } 85 } 86 87 phys_size_t initdram(int board_type) 88 { 89 return CONFIG_SYS_MEM_SIZE; 90 } 91 92 int checkboard(void) 93 { 94 enum core_card core; 95 96 malta_lcd_puts("U-Boot"); 97 puts("Board: MIPS Malta"); 98 99 core = malta_core_card(); 100 switch (core) { 101 case CORE_LV: 102 puts(" CoreLV"); 103 break; 104 105 case CORE_FPGA6: 106 puts(" CoreFPGA6"); 107 break; 108 109 default: 110 puts(" CoreUnknown"); 111 } 112 113 putc('\n'); 114 return 0; 115 } 116 117 int board_eth_init(bd_t *bis) 118 { 119 return pci_eth_init(bis); 120 } 121 122 void _machine_restart(void) 123 { 124 void __iomem *reset_base; 125 126 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 127 __raw_writel(GORESET, reset_base); 128 mdelay(1000); 129 } 130 131 int board_early_init_f(void) 132 { 133 ulong io_base; 134 135 /* choose correct PCI I/O base */ 136 switch (malta_sys_con()) { 137 case SYSCON_GT64120: 138 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); 139 break; 140 141 case SYSCON_MSC01: 142 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); 143 break; 144 145 default: 146 return -1; 147 } 148 149 set_io_port_base(io_base); 150 151 /* setup FDC37M817 super I/O controller */ 152 malta_superio_init(); 153 154 return 0; 155 } 156 157 int misc_init_r(void) 158 { 159 rtc_reset(); 160 161 return 0; 162 } 163 164 struct serial_device *default_serial_console(void) 165 { 166 switch (malta_sys_con()) { 167 case SYSCON_GT64120: 168 return &eserial1_device; 169 170 default: 171 case SYSCON_MSC01: 172 return &eserial2_device; 173 } 174 } 175 176 void pci_init_board(void) 177 { 178 pci_dev_t bdf; 179 u32 val32; 180 u8 val8; 181 182 switch (malta_sys_con()) { 183 case SYSCON_GT64120: 184 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 185 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 186 0x10000000, 0x10000000, 128 * 1024 * 1024, 187 0x00000000, 0x00000000, 0x20000); 188 break; 189 190 default: 191 case SYSCON_MSC01: 192 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), 193 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 194 MALTA_MSC01_PCIMEM_MAP, 195 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), 196 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, 197 0x00000000, MALTA_MSC01_PCIIO_SIZE); 198 break; 199 } 200 201 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 202 PCI_DEVICE_ID_INTEL_82371AB_0, 0); 203 if (bdf == -1) 204 panic("Failed to find PIIX4 PCI bridge\n"); 205 206 /* setup PCI interrupt routing */ 207 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); 208 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); 209 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); 210 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); 211 212 /* mux SERIRQ onto SERIRQ pin */ 213 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); 214 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; 215 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); 216 217 /* enable SERIRQ - Linux currently depends upon this */ 218 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); 219 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; 220 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); 221 222 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 223 PCI_DEVICE_ID_INTEL_82371AB, 0); 224 if (bdf == -1) 225 panic("Failed to find PIIX4 IDE controller\n"); 226 227 /* enable bus master & IO access */ 228 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; 229 pci_write_config_dword(bdf, PCI_COMMAND, val32); 230 231 /* set latency */ 232 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); 233 234 /* enable IDE/ATA */ 235 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, 236 PCI_CFG_PIIX4_IDETIM_IDE); 237 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, 238 PCI_CFG_PIIX4_IDETIM_IDE); 239 } 240