1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * Copyright (C) 2013 Imagination Technologies 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <ide.h> 10 #include <netdev.h> 11 #include <pci.h> 12 #include <pci_gt64120.h> 13 #include <pci_msc01.h> 14 #include <rtc.h> 15 16 #include <asm/addrspace.h> 17 #include <asm/io.h> 18 #include <asm/malta.h> 19 20 #include "superio.h" 21 22 enum core_card { 23 CORE_UNKNOWN, 24 CORE_LV, 25 CORE_FPGA6, 26 }; 27 28 enum sys_con { 29 SYSCON_UNKNOWN, 30 SYSCON_GT64120, 31 SYSCON_MSC01, 32 }; 33 34 static void malta_lcd_puts(const char *str) 35 { 36 int i; 37 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); 38 39 /* print up to 8 characters of the string */ 40 for (i = 0; i < min((int)strlen(str), 8); i++) { 41 __raw_writel(str[i], reg); 42 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 43 } 44 45 /* fill the rest of the display with spaces */ 46 for (; i < 8; i++) { 47 __raw_writel(' ', reg); 48 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 49 } 50 } 51 52 static enum core_card malta_core_card(void) 53 { 54 u32 corid, rev; 55 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); 56 57 rev = __raw_readl(reg); 58 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; 59 60 switch (corid) { 61 case MALTA_REVISION_CORID_CORE_LV: 62 return CORE_LV; 63 64 case MALTA_REVISION_CORID_CORE_FPGA6: 65 return CORE_FPGA6; 66 67 default: 68 return CORE_UNKNOWN; 69 } 70 } 71 72 static enum sys_con malta_sys_con(void) 73 { 74 switch (malta_core_card()) { 75 case CORE_LV: 76 return SYSCON_GT64120; 77 78 case CORE_FPGA6: 79 return SYSCON_MSC01; 80 81 default: 82 return SYSCON_UNKNOWN; 83 } 84 } 85 86 phys_size_t initdram(int board_type) 87 { 88 return CONFIG_SYS_MEM_SIZE; 89 } 90 91 int checkboard(void) 92 { 93 enum core_card core; 94 95 malta_lcd_puts("U-Boot"); 96 puts("Board: MIPS Malta"); 97 98 core = malta_core_card(); 99 switch (core) { 100 case CORE_LV: 101 puts(" CoreLV"); 102 break; 103 104 case CORE_FPGA6: 105 puts(" CoreFPGA6"); 106 break; 107 108 default: 109 puts(" CoreUnknown"); 110 } 111 112 putc('\n'); 113 return 0; 114 } 115 116 int board_eth_init(bd_t *bis) 117 { 118 return pci_eth_init(bis); 119 } 120 121 void _machine_restart(void) 122 { 123 void __iomem *reset_base; 124 125 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 126 __raw_writel(GORESET, reset_base); 127 mdelay(1000); 128 } 129 130 int board_early_init_f(void) 131 { 132 ulong io_base; 133 134 /* choose correct PCI I/O base */ 135 switch (malta_sys_con()) { 136 case SYSCON_GT64120: 137 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); 138 break; 139 140 case SYSCON_MSC01: 141 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); 142 break; 143 144 default: 145 return -1; 146 } 147 148 set_io_port_base(io_base); 149 150 /* setup FDC37M817 super I/O controller */ 151 malta_superio_init(); 152 153 return 0; 154 } 155 156 int misc_init_r(void) 157 { 158 rtc_reset(); 159 160 return 0; 161 } 162 163 void pci_init_board(void) 164 { 165 pci_dev_t bdf; 166 u32 val32; 167 u8 val8; 168 169 switch (malta_sys_con()) { 170 case SYSCON_GT64120: 171 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 172 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 173 0x10000000, 0x10000000, 128 * 1024 * 1024, 174 0x00000000, 0x00000000, 0x20000); 175 break; 176 177 default: 178 case SYSCON_MSC01: 179 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), 180 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 181 MALTA_MSC01_PCIMEM_MAP, 182 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), 183 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, 184 0x00000000, MALTA_MSC01_PCIIO_SIZE); 185 break; 186 } 187 188 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 189 PCI_DEVICE_ID_INTEL_82371AB_0, 0); 190 if (bdf == -1) 191 panic("Failed to find PIIX4 PCI bridge\n"); 192 193 /* setup PCI interrupt routing */ 194 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); 195 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); 196 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); 197 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); 198 199 /* mux SERIRQ onto SERIRQ pin */ 200 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); 201 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; 202 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); 203 204 /* enable SERIRQ - Linux currently depends upon this */ 205 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); 206 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; 207 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); 208 209 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 210 PCI_DEVICE_ID_INTEL_82371AB, 0); 211 if (bdf == -1) 212 panic("Failed to find PIIX4 IDE controller\n"); 213 214 /* enable bus master & IO access */ 215 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; 216 pci_write_config_dword(bdf, PCI_COMMAND, val32); 217 218 /* set latency */ 219 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); 220 221 /* enable IDE/ATA */ 222 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, 223 PCI_CFG_PIIX4_IDETIM_IDE); 224 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, 225 PCI_CFG_PIIX4_IDETIM_IDE); 226 } 227