1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * Copyright (C) 2013 Imagination Technologies 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <ide.h> 10 #include <netdev.h> 11 #include <pci.h> 12 #include <pci_gt64120.h> 13 #include <pci_msc01.h> 14 #include <rtc.h> 15 #include <serial.h> 16 17 #include <asm/addrspace.h> 18 #include <asm/io.h> 19 #include <asm/malta.h> 20 21 #include "superio.h" 22 23 enum core_card { 24 CORE_UNKNOWN, 25 CORE_LV, 26 CORE_FPGA6, 27 }; 28 29 enum sys_con { 30 SYSCON_UNKNOWN, 31 SYSCON_GT64120, 32 SYSCON_MSC01, 33 }; 34 35 static void malta_lcd_puts(const char *str) 36 { 37 int i; 38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); 39 40 /* print up to 8 characters of the string */ 41 for (i = 0; i < min((int)strlen(str), 8); i++) { 42 __raw_writel(str[i], reg); 43 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 44 } 45 46 /* fill the rest of the display with spaces */ 47 for (; i < 8; i++) { 48 __raw_writel(' ', reg); 49 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 50 } 51 } 52 53 static enum core_card malta_core_card(void) 54 { 55 u32 corid, rev; 56 57 rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); 58 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; 59 60 switch (corid) { 61 case MALTA_REVISION_CORID_CORE_LV: 62 return CORE_LV; 63 64 case MALTA_REVISION_CORID_CORE_FPGA6: 65 return CORE_FPGA6; 66 67 default: 68 return CORE_UNKNOWN; 69 } 70 } 71 72 static enum sys_con malta_sys_con(void) 73 { 74 switch (malta_core_card()) { 75 case CORE_LV: 76 return SYSCON_GT64120; 77 78 case CORE_FPGA6: 79 return SYSCON_MSC01; 80 81 default: 82 return SYSCON_UNKNOWN; 83 } 84 } 85 86 phys_size_t initdram(int board_type) 87 { 88 return CONFIG_SYS_MEM_SIZE; 89 } 90 91 int checkboard(void) 92 { 93 enum core_card core; 94 95 malta_lcd_puts("U-boot"); 96 puts("Board: MIPS Malta"); 97 98 core = malta_core_card(); 99 switch (core) { 100 case CORE_LV: 101 puts(" CoreLV"); 102 break; 103 104 case CORE_FPGA6: 105 puts(" CoreFPGA6"); 106 break; 107 108 default: 109 puts(" CoreUnknown"); 110 } 111 112 putc('\n'); 113 return 0; 114 } 115 116 int board_eth_init(bd_t *bis) 117 { 118 return pci_eth_init(bis); 119 } 120 121 void _machine_restart(void) 122 { 123 void __iomem *reset_base; 124 125 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 126 __raw_writel(GORESET, reset_base); 127 mdelay(1000); 128 } 129 130 int board_early_init_f(void) 131 { 132 void *io_base; 133 134 /* choose correct PCI I/O base */ 135 switch (malta_sys_con()) { 136 case SYSCON_GT64120: 137 io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); 138 break; 139 140 case SYSCON_MSC01: 141 io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); 142 break; 143 144 default: 145 return -1; 146 } 147 148 /* setup FDC37M817 super I/O controller */ 149 malta_superio_init(io_base); 150 151 return 0; 152 } 153 154 int misc_init_r(void) 155 { 156 rtc_reset(); 157 158 return 0; 159 } 160 161 struct serial_device *default_serial_console(void) 162 { 163 switch (malta_sys_con()) { 164 case SYSCON_GT64120: 165 return &eserial1_device; 166 167 default: 168 case SYSCON_MSC01: 169 return &eserial2_device; 170 } 171 } 172 173 void pci_init_board(void) 174 { 175 pci_dev_t bdf; 176 u32 val32; 177 u8 val8; 178 179 switch (malta_sys_con()) { 180 case SYSCON_GT64120: 181 set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); 182 183 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 184 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 185 0x10000000, 0x10000000, 128 * 1024 * 1024, 186 0x00000000, 0x00000000, 0x20000); 187 break; 188 189 default: 190 case SYSCON_MSC01: 191 set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); 192 193 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), 194 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 195 MALTA_MSC01_PCIMEM_MAP, 196 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), 197 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, 198 0x00000000, MALTA_MSC01_PCIIO_SIZE); 199 break; 200 } 201 202 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 203 PCI_DEVICE_ID_INTEL_82371AB_0, 0); 204 if (bdf == -1) 205 panic("Failed to find PIIX4 PCI bridge\n"); 206 207 /* setup PCI interrupt routing */ 208 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); 209 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); 210 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); 211 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); 212 213 /* mux SERIRQ onto SERIRQ pin */ 214 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); 215 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; 216 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); 217 218 /* enable SERIRQ - Linux currently depends upon this */ 219 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); 220 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; 221 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); 222 223 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 224 PCI_DEVICE_ID_INTEL_82371AB, 0); 225 if (bdf == -1) 226 panic("Failed to find PIIX4 IDE controller\n"); 227 228 /* enable bus master & IO access */ 229 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; 230 pci_write_config_dword(bdf, PCI_COMMAND, val32); 231 232 /* set latency */ 233 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); 234 235 /* enable IDE/ATA */ 236 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, 237 PCI_CFG_PIIX4_IDETIM_IDE); 238 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, 239 PCI_CFG_PIIX4_IDETIM_IDE); 240 } 241