1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * Copyright (C) 2013 Imagination Technologies 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <ide.h> 10 #include <netdev.h> 11 #include <pci.h> 12 #include <pci_gt64120.h> 13 #include <pci_msc01.h> 14 #include <rtc.h> 15 16 #include <asm/addrspace.h> 17 #include <asm/io.h> 18 #include <asm/malta.h> 19 20 #include "superio.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 enum core_card { 25 CORE_UNKNOWN, 26 CORE_LV, 27 CORE_FPGA6, 28 }; 29 30 enum sys_con { 31 SYSCON_UNKNOWN, 32 SYSCON_GT64120, 33 SYSCON_MSC01, 34 }; 35 36 static void malta_lcd_puts(const char *str) 37 { 38 int i; 39 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); 40 41 /* print up to 8 characters of the string */ 42 for (i = 0; i < min((int)strlen(str), 8); i++) { 43 __raw_writel(str[i], reg); 44 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 45 } 46 47 /* fill the rest of the display with spaces */ 48 for (; i < 8; i++) { 49 __raw_writel(' ', reg); 50 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; 51 } 52 } 53 54 static enum core_card malta_core_card(void) 55 { 56 u32 corid, rev; 57 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); 58 59 rev = __raw_readl(reg); 60 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; 61 62 switch (corid) { 63 case MALTA_REVISION_CORID_CORE_LV: 64 return CORE_LV; 65 66 case MALTA_REVISION_CORID_CORE_FPGA6: 67 return CORE_FPGA6; 68 69 default: 70 return CORE_UNKNOWN; 71 } 72 } 73 74 static enum sys_con malta_sys_con(void) 75 { 76 switch (malta_core_card()) { 77 case CORE_LV: 78 return SYSCON_GT64120; 79 80 case CORE_FPGA6: 81 return SYSCON_MSC01; 82 83 default: 84 return SYSCON_UNKNOWN; 85 } 86 } 87 88 int dram_init(void) 89 { 90 gd->ram_size = CONFIG_SYS_MEM_SIZE; 91 92 return 0; 93 } 94 95 int checkboard(void) 96 { 97 enum core_card core; 98 99 malta_lcd_puts("U-Boot"); 100 puts("Board: MIPS Malta"); 101 102 core = malta_core_card(); 103 switch (core) { 104 case CORE_LV: 105 puts(" CoreLV"); 106 break; 107 108 case CORE_FPGA6: 109 puts(" CoreFPGA6"); 110 break; 111 112 default: 113 puts(" CoreUnknown"); 114 } 115 116 putc('\n'); 117 return 0; 118 } 119 120 int board_eth_init(bd_t *bis) 121 { 122 return pci_eth_init(bis); 123 } 124 125 void _machine_restart(void) 126 { 127 void __iomem *reset_base; 128 129 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 130 __raw_writel(GORESET, reset_base); 131 mdelay(1000); 132 } 133 134 int board_early_init_f(void) 135 { 136 ulong io_base; 137 138 /* choose correct PCI I/O base */ 139 switch (malta_sys_con()) { 140 case SYSCON_GT64120: 141 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); 142 break; 143 144 case SYSCON_MSC01: 145 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); 146 break; 147 148 default: 149 return -1; 150 } 151 152 set_io_port_base(io_base); 153 154 /* setup FDC37M817 super I/O controller */ 155 malta_superio_init(); 156 157 return 0; 158 } 159 160 int misc_init_r(void) 161 { 162 rtc_reset(); 163 164 return 0; 165 } 166 167 void pci_init_board(void) 168 { 169 pci_dev_t bdf; 170 u32 val32; 171 u8 val8; 172 173 switch (malta_sys_con()) { 174 case SYSCON_GT64120: 175 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 176 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 177 0x10000000, 0x10000000, 128 * 1024 * 1024, 178 0x00000000, 0x00000000, 0x20000); 179 break; 180 181 default: 182 case SYSCON_MSC01: 183 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), 184 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 185 MALTA_MSC01_PCIMEM_MAP, 186 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), 187 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, 188 0x00000000, MALTA_MSC01_PCIIO_SIZE); 189 break; 190 } 191 192 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 193 PCI_DEVICE_ID_INTEL_82371AB_0, 0); 194 if (bdf == -1) 195 panic("Failed to find PIIX4 PCI bridge\n"); 196 197 /* setup PCI interrupt routing */ 198 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); 199 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); 200 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); 201 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); 202 203 /* mux SERIRQ onto SERIRQ pin */ 204 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); 205 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; 206 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); 207 208 /* enable SERIRQ - Linux currently depends upon this */ 209 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); 210 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; 211 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); 212 213 bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 214 PCI_DEVICE_ID_INTEL_82371AB, 0); 215 if (bdf == -1) 216 panic("Failed to find PIIX4 IDE controller\n"); 217 218 /* enable bus master & IO access */ 219 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; 220 pci_write_config_dword(bdf, PCI_COMMAND, val32); 221 222 /* set latency */ 223 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); 224 225 /* enable IDE/ATA */ 226 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, 227 PCI_CFG_PIIX4_IDETIM_IDE); 228 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, 229 PCI_CFG_PIIX4_IDETIM_IDE); 230 } 231