1/* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7#include <config.h> 8#include <gt64120.h> 9#include <msc01.h> 10#include <pci.h> 11 12#include <asm/addrspace.h> 13#include <asm/asm.h> 14#include <asm/regdef.h> 15#include <asm/malta.h> 16#include <asm/mipsregs.h> 17 18#ifdef CONFIG_SYS_BIG_ENDIAN 19#define CPU_TO_GT32(_x) ((_x)) 20#else 21#define CPU_TO_GT32(_x) ( \ 22 (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ 23 (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) 24#endif 25 26 .text 27 .set noreorder 28 29 .globl lowlevel_init 30lowlevel_init: 31 /* detect the core card */ 32 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) 33 lw t0, 0(t0) 34 srl t0, t0, MALTA_REVISION_CORID_SHF 35 andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ 36 MALTA_REVISION_CORID_SHF) 37 38 /* core cards using the gt64120 system controller */ 39 li t1, MALTA_REVISION_CORID_CORE_LV 40 beq t0, t1, _gt64120 41 42 /* core cards using the MSC01 system controller */ 43 li t1, MALTA_REVISION_CORID_CORE_FPGA6 44 beq t0, t1, _msc01 45 nop 46 47 /* unknown system controller */ 48 b . 49 nop 50 51 /* 52 * Load BAR registers of GT64120 as done by YAMON 53 * 54 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com> 55 * to the barebox mailing list. 56 * The subject of the original patch: 57 * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' 58 * URL: 59 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html 60 * 61 * based on write_bootloader() in qemu.git/hw/mips_malta.c 62 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details 63 */ 64_gt64120: 65 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 66 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE) 67 li t0, CPU_TO_GT32(0xdf000000) 68 sw t0, GT_ISD_OFS(t1) 69 70 /* setup MEM-to-PCI0 mapping */ 71 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE) 72 73 /* setup PCI0 io window to 0x18000000-0x181fffff */ 74 li t0, CPU_TO_GT32(0xc0000000) 75 sw t0, GT_PCI0IOLD_OFS(t1) 76 li t0, CPU_TO_GT32(0x40000000) 77 sw t0, GT_PCI0IOHD_OFS(t1) 78 79 /* setup PCI0 mem windows */ 80 li t0, CPU_TO_GT32(0x80000000) 81 sw t0, GT_PCI0M0LD_OFS(t1) 82 li t0, CPU_TO_GT32(0x3f000000) 83 sw t0, GT_PCI0M0HD_OFS(t1) 84 85 li t0, CPU_TO_GT32(0xc1000000) 86 sw t0, GT_PCI0M1LD_OFS(t1) 87 li t0, CPU_TO_GT32(0x5e000000) 88 sw t0, GT_PCI0M1HD_OFS(t1) 89 90 jr ra 91 nop 92 93 /* 94 * 95 */ 96_msc01: 97 /* setup peripheral bus controller clock divide */ 98 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE) 99 li t1, 0x1 << MSC01_PBC_CLKCFG_SHF 100 sw t1, MSC01_PBC_CLKCFG_OFS(t0) 101 102 /* tweak peripheral bus controller timings */ 103 li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ 104 (0x1 << MSC01_PBC_CS0TIM_CAT_SHF) 105 sw t1, MSC01_PBC_CS0TIM_OFS(t0) 106 li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ 107 (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ 108 (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ 109 (0x2 << MSC01_PBC_CS0RW_WAT_SHF) 110 sw t1, MSC01_PBC_CS0RW_OFS(t0) 111 lw t1, MSC01_PBC_CS0CFG_OFS(t0) 112 li t2, MSC01_PBC_CS0CFG_DTYP_MSK 113 and t1, t2 114 ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ 115 (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ 116 (0x10 << MSC01_PBC_CS0CFG_WS_SHF) 117 sw t1, MSC01_PBC_CS0CFG_OFS(t0) 118 119 /* setup basic address decode */ 120 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) 121 li t1, 0x0 122 li t2, -CONFIG_SYS_MEM_SIZE 123 sw t1, MSC01_BIU_MCBAS1L_OFS(t0) 124 sw t2, MSC01_BIU_MCMSK1L_OFS(t0) 125 sw t1, MSC01_BIU_MCBAS2L_OFS(t0) 126 sw t2, MSC01_BIU_MCMSK2L_OFS(t0) 127 128 /* initialise IP1 - unused */ 129 li t1, MALTA_MSC01_IP1_BASE 130 li t2, -MALTA_MSC01_IP1_SIZE 131 sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) 132 sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) 133 sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) 134 sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) 135 136 /* initialise IP2 - PCI */ 137 li t1, MALTA_MSC01_IP2_BASE1 138 li t2, -MALTA_MSC01_IP2_SIZE1 139 sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) 140 sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) 141 li t1, MALTA_MSC01_IP2_BASE2 142 li t2, -MALTA_MSC01_IP2_SIZE2 143 sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) 144 sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) 145 146 /* initialise IP3 - peripheral bus controller */ 147 li t1, MALTA_MSC01_IP3_BASE 148 li t2, -MALTA_MSC01_IP3_SIZE 149 sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) 150 sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) 151 sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) 152 sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) 153 154 /* setup PCI memory */ 155 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE) 156 li t1, MALTA_MSC01_PCIMEM_BASE 157 li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK 158 li t3, MALTA_MSC01_PCIMEM_MAP 159 sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) 160 sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) 161 sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) 162 163 /* setup PCI I/O */ 164 li t1, MALTA_MSC01_PCIIO_BASE 165 li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK 166 li t3, MALTA_MSC01_PCIIO_MAP 167 sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) 168 sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) 169 sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) 170 171 /* setup PCI_BAR0 memory window */ 172 li t1, -CONFIG_SYS_MEM_SIZE 173 sw t1, MSC01_PCI_BAR0_OFS(t0) 174 175 /* setup PCI to SysCon/CPU translation */ 176 sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) 177 sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) 178 179 /* setup PCI vendor & device IDs */ 180 li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ 181 (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) 182 sw t1, MSC01_PCI_HEAD0_OFS(t0) 183 184 /* setup PCI subsystem vendor & device IDs */ 185 sw t1, MSC01_PCI_HEAD11_OFS(t0) 186 187 /* setup PCI class, revision */ 188 li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ 189 (0x1 << MSC01_PCI_HEAD2_REV_SHF) 190 sw t1, MSC01_PCI_HEAD2_OFS(t0) 191 192 /* ensure a sane setup */ 193 sw zero, MSC01_PCI_HEAD3_OFS(t0) 194 sw zero, MSC01_PCI_HEAD4_OFS(t0) 195 sw zero, MSC01_PCI_HEAD5_OFS(t0) 196 sw zero, MSC01_PCI_HEAD6_OFS(t0) 197 sw zero, MSC01_PCI_HEAD7_OFS(t0) 198 sw zero, MSC01_PCI_HEAD8_OFS(t0) 199 sw zero, MSC01_PCI_HEAD9_OFS(t0) 200 sw zero, MSC01_PCI_HEAD10_OFS(t0) 201 sw zero, MSC01_PCI_HEAD12_OFS(t0) 202 sw zero, MSC01_PCI_HEAD13_OFS(t0) 203 sw zero, MSC01_PCI_HEAD14_OFS(t0) 204 sw zero, MSC01_PCI_HEAD15_OFS(t0) 205 206 /* setup PCI command register */ 207 li t1, (PCI_COMMAND_FAST_BACK | \ 208 PCI_COMMAND_SERR | \ 209 PCI_COMMAND_PARITY | \ 210 PCI_COMMAND_MASTER | \ 211 PCI_COMMAND_MEMORY) 212 sw t1, MSC01_PCI_HEAD1_OFS(t0) 213 214 /* setup PCI byte swapping */ 215#ifdef CONFIG_SYS_BIG_ENDIAN 216 li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ 217 (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) 218 sw t1, MSC01_PCI_SWAP_OFS(t0) 219#else 220 sw zero, MSC01_PCI_SWAP_OFS(t0) 221#endif 222 223 /* enable PCI host configuration cycles */ 224 lw t1, MSC01_PCI_CFG_OFS(t0) 225 li t2, MSC01_PCI_CFG_RA_MSK | \ 226 MSC01_PCI_CFG_G_MSK | \ 227 MSC01_PCI_CFG_EN_MSK 228 or t1, t1, t2 229 sw t1, MSC01_PCI_CFG_OFS(t0) 230 231 jr ra 232 nop 233