1/* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7#include <config.h> 8#include <gt64120.h> 9#include <msc01.h> 10#include <pci.h> 11 12#include <asm/addrspace.h> 13#include <asm/regdef.h> 14#include <asm/malta.h> 15#include <asm/mipsregs.h> 16 17#ifdef CONFIG_SYS_BIG_ENDIAN 18#define CPU_TO_GT32(_x) ((_x)) 19#else 20#define CPU_TO_GT32(_x) ( \ 21 (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ 22 (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) 23#endif 24 25 .text 26 .set noreorder 27 28 .globl lowlevel_init 29lowlevel_init: 30 /* disable any L2 cache for now */ 31 sync 32 mfc0 t0, CP0_CONFIG, 2 33 ori t0, t0, 0x1 << 12 34 mtc0 t0, CP0_CONFIG, 2 35 36 /* detect the core card */ 37 li t0, KSEG1ADDR(MALTA_REVISION) 38 lw t0, 0(t0) 39 srl t0, t0, MALTA_REVISION_CORID_SHF 40 andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ 41 MALTA_REVISION_CORID_SHF) 42 43 /* core cards using the gt64120 system controller */ 44 li t1, MALTA_REVISION_CORID_CORE_LV 45 beq t0, t1, _gt64120 46 47 /* core cards using the MSC01 system controller */ 48 li t1, MALTA_REVISION_CORID_CORE_FPGA6 49 beq t0, t1, _msc01 50 nop 51 52 /* unknown system controller */ 53 b . 54 nop 55 56 /* 57 * Load BAR registers of GT64120 as done by YAMON 58 * 59 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com> 60 * to the barebox mailing list. 61 * The subject of the original patch: 62 * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' 63 * URL: 64 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html 65 * 66 * based on write_bootloader() in qemu.git/hw/mips_malta.c 67 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details 68 */ 69_gt64120: 70 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 71 li t1, KSEG1ADDR(GT_DEF_BASE) 72 li t0, CPU_TO_GT32(0xdf000000) 73 sw t0, GT_ISD_OFS(t1) 74 75 /* setup MEM-to-PCI0 mapping */ 76 li t1, KSEG1ADDR(MALTA_GT_BASE) 77 78 /* setup PCI0 io window to 0x18000000-0x181fffff */ 79 li t0, CPU_TO_GT32(0xc0000000) 80 sw t0, GT_PCI0IOLD_OFS(t1) 81 li t0, CPU_TO_GT32(0x40000000) 82 sw t0, GT_PCI0IOHD_OFS(t1) 83 84 /* setup PCI0 mem windows */ 85 li t0, CPU_TO_GT32(0x80000000) 86 sw t0, GT_PCI0M0LD_OFS(t1) 87 li t0, CPU_TO_GT32(0x3f000000) 88 sw t0, GT_PCI0M0HD_OFS(t1) 89 90 li t0, CPU_TO_GT32(0xc1000000) 91 sw t0, GT_PCI0M1LD_OFS(t1) 92 li t0, CPU_TO_GT32(0x5e000000) 93 sw t0, GT_PCI0M1HD_OFS(t1) 94 95 jr ra 96 nop 97 98 /* 99 * 100 */ 101_msc01: 102 /* setup peripheral bus controller clock divide */ 103 li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) 104 li t1, 0x1 << MSC01_PBC_CLKCFG_SHF 105 sw t1, MSC01_PBC_CLKCFG_OFS(t0) 106 107 /* tweak peripheral bus controller timings */ 108 li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ 109 (0x1 << MSC01_PBC_CS0TIM_CAT_SHF) 110 sw t1, MSC01_PBC_CS0TIM_OFS(t0) 111 li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ 112 (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ 113 (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ 114 (0x2 << MSC01_PBC_CS0RW_WAT_SHF) 115 sw t1, MSC01_PBC_CS0RW_OFS(t0) 116 lw t1, MSC01_PBC_CS0CFG_OFS(t0) 117 li t2, MSC01_PBC_CS0CFG_DTYP_MSK 118 and t1, t2 119 ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ 120 (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ 121 (0x10 << MSC01_PBC_CS0CFG_WS_SHF) 122 sw t1, MSC01_PBC_CS0CFG_OFS(t0) 123 124 /* setup basic address decode */ 125 li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) 126 li t1, 0x0 127 li t2, -CONFIG_SYS_MEM_SIZE 128 sw t1, MSC01_BIU_MCBAS1L_OFS(t0) 129 sw t2, MSC01_BIU_MCMSK1L_OFS(t0) 130 sw t1, MSC01_BIU_MCBAS2L_OFS(t0) 131 sw t2, MSC01_BIU_MCMSK2L_OFS(t0) 132 133 /* initialise IP1 - unused */ 134 li t1, MALTA_MSC01_IP1_BASE 135 li t2, -MALTA_MSC01_IP1_SIZE 136 sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) 137 sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) 138 sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) 139 sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) 140 141 /* initialise IP2 - PCI */ 142 li t1, MALTA_MSC01_IP2_BASE1 143 li t2, -MALTA_MSC01_IP2_SIZE1 144 sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) 145 sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) 146 li t1, MALTA_MSC01_IP2_BASE2 147 li t2, -MALTA_MSC01_IP2_SIZE2 148 sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) 149 sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) 150 151 /* initialise IP3 - peripheral bus controller */ 152 li t1, MALTA_MSC01_IP3_BASE 153 li t2, -MALTA_MSC01_IP3_SIZE 154 sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) 155 sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) 156 sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) 157 sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) 158 159 /* setup PCI memory */ 160 li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) 161 li t1, MALTA_MSC01_PCIMEM_BASE 162 li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK 163 li t3, MALTA_MSC01_PCIMEM_MAP 164 sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) 165 sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) 166 sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) 167 168 /* setup PCI I/O */ 169 li t1, MALTA_MSC01_PCIIO_BASE 170 li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK 171 li t3, MALTA_MSC01_PCIIO_MAP 172 sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) 173 sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) 174 sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) 175 176 /* setup PCI_BAR0 memory window */ 177 li t1, -CONFIG_SYS_MEM_SIZE 178 sw t1, MSC01_PCI_BAR0_OFS(t0) 179 180 /* setup PCI to SysCon/CPU translation */ 181 sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) 182 sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) 183 184 /* setup PCI vendor & device IDs */ 185 li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ 186 (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) 187 sw t1, MSC01_PCI_HEAD0_OFS(t0) 188 189 /* setup PCI subsystem vendor & device IDs */ 190 sw t1, MSC01_PCI_HEAD11_OFS(t0) 191 192 /* setup PCI class, revision */ 193 li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ 194 (0x1 << MSC01_PCI_HEAD2_REV_SHF) 195 sw t1, MSC01_PCI_HEAD2_OFS(t0) 196 197 /* ensure a sane setup */ 198 sw zero, MSC01_PCI_HEAD3_OFS(t0) 199 sw zero, MSC01_PCI_HEAD4_OFS(t0) 200 sw zero, MSC01_PCI_HEAD5_OFS(t0) 201 sw zero, MSC01_PCI_HEAD6_OFS(t0) 202 sw zero, MSC01_PCI_HEAD7_OFS(t0) 203 sw zero, MSC01_PCI_HEAD8_OFS(t0) 204 sw zero, MSC01_PCI_HEAD9_OFS(t0) 205 sw zero, MSC01_PCI_HEAD10_OFS(t0) 206 sw zero, MSC01_PCI_HEAD12_OFS(t0) 207 sw zero, MSC01_PCI_HEAD13_OFS(t0) 208 sw zero, MSC01_PCI_HEAD14_OFS(t0) 209 sw zero, MSC01_PCI_HEAD15_OFS(t0) 210 211 /* setup PCI command register */ 212 li t1, (PCI_COMMAND_FAST_BACK | \ 213 PCI_COMMAND_SERR | \ 214 PCI_COMMAND_PARITY | \ 215 PCI_COMMAND_MASTER | \ 216 PCI_COMMAND_MEMORY) 217 sw t1, MSC01_PCI_HEAD1_OFS(t0) 218 219 /* setup PCI byte swapping */ 220#ifdef CONFIG_SYS_BIG_ENDIAN 221 li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ 222 (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) 223 sw t1, MSC01_PCI_SWAP_OFS(t0) 224#else 225 sw zero, MSC01_PCI_SWAP_OFS(t0) 226#endif 227 228 /* enable PCI host configuration cycles */ 229 lw t1, MSC01_PCI_CFG_OFS(t0) 230 li t2, MSC01_PCI_CFG_RA_MSK | \ 231 MSC01_PCI_CFG_G_MSK | \ 232 MSC01_PCI_CFG_EN_MSK 233 or t1, t1, t2 234 sw t1, MSC01_PCI_CFG_OFS(t0) 235 236 jr ra 237 nop 238