1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * CI20 setup code 4 * 5 * Copyright (c) 2013 Imagination Technologies 6 * Author: Paul Burton <paul.burton@imgtec.com> 7 */ 8 9 #include <common.h> 10 #include <environment.h> 11 #include <net.h> 12 #include <netdev.h> 13 #include <asm/io.h> 14 #include <asm/gpio.h> 15 #include <mach/jz4780.h> 16 #include <mach/jz4780_dram.h> 17 #include <mach/jz4780_gpio.h> 18 19 struct ci20_otp { 20 u32 serial_number; 21 u32 date; 22 u8 manufacturer[2]; 23 u8 mac[6]; 24 } __packed; 25 26 static void ci20_mux_mmc(void) 27 { 28 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; 29 30 /* setup MSC1 pins */ 31 writel(0x30f00000, gpio_regs + GPIO_PXINTC(4)); 32 writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4)); 33 writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4)); 34 writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4)); 35 writel(0x30f00000, gpio_regs + GPIO_PXPENC(4)); 36 jz4780_clk_ungate_mmc(); 37 } 38 39 #ifndef CONFIG_SPL_BUILD 40 41 static void ci20_mux_eth(void) 42 { 43 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; 44 45 #ifdef CONFIG_NAND 46 /* setup pins (some already setup for NAND) */ 47 writel(0x04030000, gpio_regs + GPIO_PXINTC(0)); 48 writel(0x04030000, gpio_regs + GPIO_PXMASKC(0)); 49 writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0)); 50 writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0)); 51 writel(0x04030000, gpio_regs + GPIO_PXPENS(0)); 52 #else 53 /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */ 54 writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0)); 55 writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0)); 56 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0)); 57 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0)); 58 writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0)); 59 writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); 60 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); 61 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); 62 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); 63 writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); 64 #endif 65 } 66 67 static void ci20_mux_jtag(void) 68 { 69 #ifdef CONFIG_JTAG 70 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; 71 72 /* enable JTAG */ 73 writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); 74 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); 75 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); 76 writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0)); 77 #endif 78 } 79 80 static void ci20_mux_nand(void) 81 { 82 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; 83 84 /* setup pins */ 85 writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0)); 86 writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0)); 87 writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0)); 88 writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0)); 89 writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0)); 90 writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); 91 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); 92 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); 93 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); 94 writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); 95 96 /* FRB0_N */ 97 jz47xx_gpio_direction_input(JZ_GPIO(0, 20)); 98 writel(20, gpio_regs + GPIO_PXPENS(0)); 99 100 /* disable write protect */ 101 jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1); 102 } 103 104 static void ci20_mux_uart(void) 105 { 106 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; 107 108 /* UART0 */ 109 writel(0x9, gpio_regs + GPIO_PXINTC(5)); 110 writel(0x9, gpio_regs + GPIO_PXMASKC(5)); 111 writel(0x9, gpio_regs + GPIO_PXPAT1C(5)); 112 writel(0x9, gpio_regs + GPIO_PXPAT0C(5)); 113 writel(0x9, gpio_regs + GPIO_PXPENC(5)); 114 jz4780_clk_ungate_uart(0); 115 116 /* UART 1 and 2 */ 117 jz4780_clk_ungate_uart(1); 118 jz4780_clk_ungate_uart(2); 119 120 #ifndef CONFIG_JTAG 121 /* UART3 */ 122 writel(1 << 12, gpio_regs + GPIO_PXINTC(3)); 123 writel(1 << 12, gpio_regs + GPIO_PXMASKS(3)); 124 writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3)); 125 writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3)); 126 writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); 127 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); 128 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); 129 writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0)); 130 writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0)); 131 jz4780_clk_ungate_uart(3); 132 #endif 133 134 /* UART4 */ 135 writel(0x100400, gpio_regs + GPIO_PXINTC(2)); 136 writel(0x100400, gpio_regs + GPIO_PXMASKC(2)); 137 writel(0x100400, gpio_regs + GPIO_PXPAT1S(2)); 138 writel(0x100400, gpio_regs + GPIO_PXPAT0C(2)); 139 writel(0x100400, gpio_regs + GPIO_PXPENC(2)); 140 jz4780_clk_ungate_uart(4); 141 } 142 143 int board_early_init_f(void) 144 { 145 ci20_mux_jtag(); 146 ci20_mux_uart(); 147 148 ci20_mux_eth(); 149 ci20_mux_mmc(); 150 ci20_mux_nand(); 151 152 /* SYS_POWER_IND high (LED blue, VBUS off) */ 153 jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0); 154 155 /* LEDs off */ 156 jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0); 157 jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0); 158 jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0); 159 jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0); 160 161 return 0; 162 } 163 164 int misc_init_r(void) 165 { 166 const u32 efuse_clk = jz4780_clk_get_efuse_clk(); 167 struct ci20_otp otp; 168 char manufacturer[3]; 169 170 /* Read the board OTP data */ 171 jz4780_efuse_init(efuse_clk); 172 jz4780_efuse_read(0x18, 16, (u8 *)&otp); 173 174 /* Set MAC address */ 175 if (!is_valid_ethaddr(otp.mac)) { 176 /* no MAC assigned, generate one from the unique chip ID */ 177 jz4780_efuse_read(0x8, 4, &otp.mac[0]); 178 jz4780_efuse_read(0x12, 2, &otp.mac[4]); 179 otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01; 180 } 181 eth_env_set_enetaddr("ethaddr", otp.mac); 182 183 /* Put other board information into the environment */ 184 env_set_ulong("serial#", otp.serial_number); 185 env_set_ulong("board_date", otp.date); 186 manufacturer[0] = otp.manufacturer[0]; 187 manufacturer[1] = otp.manufacturer[1]; 188 manufacturer[2] = 0; 189 env_set("board_mfr", manufacturer); 190 191 return 0; 192 } 193 194 #ifdef CONFIG_DRIVER_DM9000 195 int board_eth_init(bd_t *bis) 196 { 197 /* Enable clock */ 198 jz4780_clk_ungate_ethernet(); 199 200 /* Enable power (PB25) */ 201 jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1); 202 203 /* Reset (PF12) */ 204 mdelay(10); 205 jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0); 206 mdelay(10); 207 jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1); 208 mdelay(10); 209 210 return dm9000_initialize(bis); 211 } 212 #endif /* CONFIG_DRIVER_DM9000 */ 213 #endif 214 215 static u8 ci20_revision(void) 216 { 217 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; 218 int val; 219 220 jz47xx_gpio_direction_input(JZ_GPIO(2, 18)); 221 jz47xx_gpio_direction_input(JZ_GPIO(2, 19)); 222 223 /* Enable pullups */ 224 writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2)); 225 226 /* Read PC18/19 for version */ 227 val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) | 228 ((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1); 229 230 if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */ 231 return 1; 232 if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */ 233 return 2; 234 235 return 0; 236 } 237 238 int dram_init(void) 239 { 240 gd->ram_size = sdram_size(0) + sdram_size(1); 241 return 0; 242 } 243 244 /* U-Boot common routines */ 245 int checkboard(void) 246 { 247 printf("Board: Creator CI20 (rev.%d)\n", ci20_revision()); 248 return 0; 249 } 250 251 #ifdef CONFIG_SPL_BUILD 252 253 #if defined(CONFIG_SPL_MMC_SUPPORT) 254 int board_mmc_init(bd_t *bd) 255 { 256 ci20_mux_mmc(); 257 return jz_mmc_init((void __iomem *)MSC0_BASE); 258 } 259 #endif 260 261 static const struct jz4780_ddr_config K4B2G0846Q_48_config = { 262 .timing = { 263 (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) | 264 (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT), 265 266 (4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) | 267 (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT), 268 269 (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) | 270 (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) | 271 (21 << DDRC_TIMING3_TRC_BIT), 272 273 (31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) | 274 (4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) | 275 (8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT), 276 277 (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) | 278 (4 << DDRC_TIMING5_TWDLAT_BIT), 279 280 (25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) | 281 (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT), 282 }, 283 284 /* PHY */ 285 /* Mode Register 0 */ 286 .mr0 = 0x420, 287 #ifdef SDRAM_DISABLE_DLL 288 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE), 289 #else 290 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS), 291 #endif 292 293 .ptr0 = 0x002000d4, 294 .ptr1 = 0x02230d40, 295 .ptr2 = 0x04013880, 296 297 .dtpr0 = 0x2a8f6690, 298 .dtpr1 = 0x00400860, 299 .dtpr2 = 0x10042a00, 300 301 .pullup = 0x0b, 302 .pulldn = 0x0b, 303 }; 304 305 static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = { 306 .timing = { 307 (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) | 308 (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT), 309 310 (4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) | 311 (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT), 312 313 (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) | 314 (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) | 315 (22 << DDRC_TIMING3_TRC_BIT), 316 317 (42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) | 318 (4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) | 319 (3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT), 320 321 (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) | 322 (4 << DDRC_TIMING5_TWDLAT_BIT), 323 324 (25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) | 325 (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT), 326 }, 327 328 /* PHY */ 329 /* Mode Register 0 */ 330 .mr0 = 0x420, 331 #ifdef SDRAM_DISABLE_DLL 332 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE), 333 #else 334 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS), 335 #endif 336 337 .ptr0 = 0x002000d4, 338 .ptr1 = 0x02d30d40, 339 .ptr2 = 0x04013880, 340 341 .dtpr0 = 0x2c906690, 342 .dtpr1 = 0x005608a0, 343 .dtpr2 = 0x10042a00, 344 345 .pullup = 0x0e, 346 .pulldn = 0x0e, 347 }; 348 349 #if (CONFIG_SYS_MHZ != 1200) 350 #error No DDR configuration for CPU speed 351 #endif 352 353 const struct jz4780_ddr_config *jz4780_get_ddr_config(void) 354 { 355 const int board_revision = ci20_revision(); 356 357 if (board_revision == 2) 358 return &K4B2G0846Q_48_config; 359 else /* Fall back to H5TQ2G83CFR RAM */ 360 return &H5TQ2G83CFR_48_config; 361 } 362 #endif 363