1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Muxing for Gumstix Pepper and AM335x-based boards 4 * 5 * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ 6 */ 7 #include <common.h> 8 #include <asm/arch/sys_proto.h> 9 #include <asm/arch/hardware.h> 10 #include <asm/arch/mux.h> 11 #include <asm/io.h> 12 #include <i2c.h> 13 #include "board.h" 14 15 static struct module_pin_mux uart0_pin_mux[] = { 16 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 17 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 18 {-1}, 19 }; 20 21 static struct module_pin_mux mmc0_pin_mux[] = { 22 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 23 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 24 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 25 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 26 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 27 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 28 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 29 {-1}, 30 }; 31 32 static struct module_pin_mux i2c0_pin_mux[] = { 33 /* I2C_DATA */ 34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 35 /* I2C_SCLK */ 36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, 37 {-1}, 38 }; 39 40 static struct module_pin_mux rgmii1_pin_mux[] = { 41 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ 42 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 43 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ 44 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ 45 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ 46 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ 47 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ 48 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 49 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 50 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 51 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 52 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 53 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 54 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 55 {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */ 56 {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */ 57 {OFFSET(xdma_event_intr1), MODE(3)}, 58 {-1}, 59 }; 60 61 void enable_uart0_pin_mux(void) 62 { 63 configure_module_pin_mux(uart0_pin_mux); 64 } 65 66 void enable_i2c0_pin_mux(void) 67 { 68 configure_module_pin_mux(i2c0_pin_mux); 69 } 70 71 /* 72 * Do board-specific muxes. 73 */ 74 void enable_board_pin_mux(void) 75 { 76 /* I2C0 */ 77 configure_module_pin_mux(i2c0_pin_mux); 78 /* SD Card */ 79 configure_module_pin_mux(mmc0_pin_mux); 80 /* Ethernet pinmux. */ 81 configure_module_pin_mux(rgmii1_pin_mux); 82 } 83