1 /* 2 * Board functions for Gumstix Pepper and AM335x-based boards 3 * 4 * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ 5 * Based on board/ti/am335x/board.c from Texas Instruments, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <errno.h> 12 #include <spl.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/omap.h> 16 #include <asm/arch/ddr_defs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/mmc_host_def.h> 20 #include <asm/arch/sys_proto.h> 21 #include <asm/arch/mem.h> 22 #include <asm/io.h> 23 #include <asm/emif.h> 24 #include <asm/gpio.h> 25 #include <i2c.h> 26 #include <miiphy.h> 27 #include <cpsw.h> 28 #include <power/tps65217.h> 29 #include <environment.h> 30 #include <watchdog.h> 31 #include "board.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #ifdef CONFIG_SPL_BUILD 36 static const struct ddr_data ddr2_data = { 37 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 38 (MT47H128M16RT25E_RD_DQS<<20) | 39 (MT47H128M16RT25E_RD_DQS<<10) | 40 (MT47H128M16RT25E_RD_DQS<<0)), 41 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 42 (MT47H128M16RT25E_WR_DQS<<20) | 43 (MT47H128M16RT25E_WR_DQS<<10) | 44 (MT47H128M16RT25E_WR_DQS<<0)), 45 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 46 (MT47H128M16RT25E_PHY_WRLVL<<20) | 47 (MT47H128M16RT25E_PHY_WRLVL<<10) | 48 (MT47H128M16RT25E_PHY_WRLVL<<0)), 49 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 50 (MT47H128M16RT25E_PHY_GATELVL<<20) | 51 (MT47H128M16RT25E_PHY_GATELVL<<10) | 52 (MT47H128M16RT25E_PHY_GATELVL<<0)), 53 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 54 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 55 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 56 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 57 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 58 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 59 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 60 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 61 }; 62 63 static const struct cmd_control ddr2_cmd_ctrl_data = { 64 .cmd0csratio = MT47H128M16RT25E_RATIO, 65 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 66 67 .cmd1csratio = MT47H128M16RT25E_RATIO, 68 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 69 70 .cmd2csratio = MT47H128M16RT25E_RATIO, 71 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 72 }; 73 74 static const struct emif_regs ddr2_emif_reg_data = { 75 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 76 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 77 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 78 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 79 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 80 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 81 }; 82 83 #ifdef CONFIG_SPL_OS_BOOT 84 int spl_start_uboot(void) 85 { 86 /* break into full u-boot on 'c' */ 87 return serial_tstc() && serial_getc() == 'c'; 88 } 89 #endif 90 91 #define OSC (V_OSCK/1000000) 92 const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; 93 94 const struct dpll_params *get_dpll_ddr_params(void) 95 { 96 return &dpll_ddr; 97 } 98 99 void set_uart_mux_conf(void) 100 { 101 enable_uart0_pin_mux(); 102 } 103 104 void set_mux_conf_regs(void) 105 { 106 enable_board_pin_mux(); 107 } 108 109 const struct ctrl_ioregs ioregs = { 110 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 111 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 112 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 113 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 114 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 115 }; 116 117 void sdram_init(void) 118 { 119 config_ddr(266, &ioregs, &ddr2_data, 120 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 121 } 122 #endif 123 124 int board_init(void) 125 { 126 #if defined(CONFIG_HW_WATCHDOG) 127 hw_watchdog_init(); 128 #endif 129 130 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 131 gpmc_init(); 132 133 return 0; 134 } 135 136 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 137 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 138 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 139 140 static void cpsw_control(int enabled) 141 { 142 /* VTP can be added here */ 143 144 return; 145 } 146 147 static struct cpsw_slave_data cpsw_slaves[] = { 148 { 149 .slave_reg_ofs = 0x208, 150 .sliver_reg_ofs = 0xd80, 151 .phy_addr = 0, 152 .phy_if = PHY_INTERFACE_MODE_RGMII, 153 }, 154 }; 155 156 static struct cpsw_platform_data cpsw_data = { 157 .mdio_base = CPSW_MDIO_BASE, 158 .cpsw_base = CPSW_BASE, 159 .mdio_div = 0xff, 160 .channels = 8, 161 .cpdma_reg_ofs = 0x800, 162 .slaves = 1, 163 .slave_data = cpsw_slaves, 164 .ale_reg_ofs = 0xd00, 165 .ale_entries = 1024, 166 .host_port_reg_ofs = 0x108, 167 .hw_stats_reg_ofs = 0x900, 168 .bd_ram_ofs = 0x2000, 169 .mac_control = (1 << 5), 170 .control = cpsw_control, 171 .host_port_num = 0, 172 .version = CPSW_CTRL_VERSION_2, 173 }; 174 175 int board_eth_init(bd_t *bis) 176 { 177 int rv, n = 0; 178 uint8_t mac_addr[6]; 179 uint32_t mac_hi, mac_lo; 180 const char *devname; 181 182 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 183 /* try reading mac address from efuse */ 184 mac_lo = readl(&cdev->macid0l); 185 mac_hi = readl(&cdev->macid0h); 186 mac_addr[0] = mac_hi & 0xFF; 187 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 188 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 189 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 190 mac_addr[4] = mac_lo & 0xFF; 191 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 192 if (is_valid_ether_addr(mac_addr)) 193 eth_setenv_enetaddr("ethaddr", mac_addr); 194 } 195 196 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 197 198 rv = cpsw_register(&cpsw_data); 199 if (rv < 0) 200 printf("Error %d registering CPSW switch\n", rv); 201 else 202 n += rv; 203 204 /* 205 * 206 * CPSW RGMII Internal Delay Mode is not supported in all PVT 207 * operating points. So we must set the TX clock delay feature 208 * in the KSZ9021 PHY. Since we only support a single ethernet 209 * device in U-Boot, we only do this for the current instance. 210 */ 211 devname = miiphy_get_current_dev(); 212 /* max rx/tx clock delay, min rx/tx control delay */ 213 miiphy_write(devname, 0x0, 0x0b, 0x8104); 214 miiphy_write(devname, 0x0, 0xc, 0xa0a0); 215 216 /* min rx data delay */ 217 miiphy_write(devname, 0x0, 0x0b, 0x8105); 218 miiphy_write(devname, 0x0, 0x0c, 0x0000); 219 220 /* min tx data delay */ 221 miiphy_write(devname, 0x0, 0x0b, 0x8106); 222 miiphy_write(devname, 0x0, 0x0c, 0x0000); 223 224 return n; 225 } 226 #endif 227