1 /* 2 * (C) Copyright 2012 3 * Gumstix Incorporated, <www.gumstix.com> 4 * Maintainer: Ash Charles <ash@gumstix.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 #ifndef _DUOVERO_MUX_DATA_H_ 9 #define _DUOVERO_MUX_DATA_H_ 10 11 #include <asm/arch/mux_omap4.h> 12 13 const struct pad_conf_entry core_padconf_array_essential[] = { 14 {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ 15 {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ 16 {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ 17 {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ 18 {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ 19 {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ 20 {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ 21 {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ 22 {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ 23 {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ 24 {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ 25 {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ 26 {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ 27 {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ 28 {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ 29 {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ 30 {UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */ 31 {UART3_TX_IRTX, (M0)} /* uart3_tx */ 32 }; 33 34 const struct pad_conf_entry wkup_padconf_array_essential[] = { 35 {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ 36 {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ 37 {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ 38 }; 39 40 const struct pad_conf_entry core_padconf_array_non_essential[] = { 41 {GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */ 42 {GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */ 43 {GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */ 44 {GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */ 45 {GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */ 46 {GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */ 47 {GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */ 48 {GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */ 49 {GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */ 50 {GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */ 51 {GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */ 52 {GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */ 53 {GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */ 54 {GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */ 55 {GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */ 56 {GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */ 57 {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */ 58 {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */ 59 {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */ 60 {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */ 61 {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */ 62 {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */ 63 {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */ 64 {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */ 65 {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */ 66 {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */ 67 {GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */ 68 {GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */ 69 {GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */ 70 {GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */ 71 {C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */ 72 {C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */ 73 {GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */ 74 {GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */ 75 {GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */ 76 {GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */ 77 {GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */ 78 {GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */ 79 {GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */ 80 {GPMC_NOE, (PTU | M0)}, /* gpmc_noe */ 81 {GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */ 82 {HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */ 83 {HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */ 84 {HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */ 85 {HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */ 86 {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ 87 {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ 88 {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ 89 {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ 90 {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ 91 {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ 92 {CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */ 93 {CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */ 94 {CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */ 95 {CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */ 96 {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ 97 {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ 98 {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ 99 {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ 100 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ 101 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ 102 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ 103 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ 104 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ 105 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ 106 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ 107 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ 108 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ 109 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ 110 {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ 111 {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ 112 {USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */ 113 {USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */ 114 {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ 115 {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ 116 {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ 117 {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ 118 {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ 119 {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ 120 {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ 121 {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ 122 {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ 123 {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ 124 {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ 125 {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ 126 {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ 127 {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ 128 {UART2_RTS, (M0)}, /* uart2_rts */ 129 {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ 130 {UART2_TX, (M0)}, /* uart2_tx */ 131 {HDQ_SIO, (M0)}, /* hdq-sio */ 132 {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ 133 {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ 134 {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ 135 {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ 136 {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */ 137 {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */ 138 {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ 139 {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ 140 {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ 141 {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ 142 {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ 143 {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ 144 {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ 145 {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ 146 {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ 147 {UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */ 148 {UART4_TX, (M0)}, /* uart4_tx */ 149 {USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */ 150 {USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */ 151 {USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */ 152 {USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/ 153 {USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */ 154 {USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */ 155 {USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */ 156 {USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */ 157 {USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */ 158 {USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/ 159 {USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */ 160 {USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */ 161 {USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */ 162 {USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */ 163 {UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */ 164 {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ 165 {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ 166 {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ 167 {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ 168 {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ 169 {SYS_BOOT0, (M0)}, /* sys_boot0 */ 170 {SYS_BOOT1, (M0)}, /* sys_boot1 */ 171 {SYS_BOOT2, (M0)}, /* sys_boot2 */ 172 {SYS_BOOT3, (M0)}, /* sys_boot3 */ 173 {SYS_BOOT4, (M0)}, /* sys_boot4 */ 174 {SYS_BOOT5, (M0)}, /* sys_boot5 */ 175 {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ 176 {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ 177 {DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */ 178 {DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */ 179 {DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */ 180 {DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */ 181 }; 182 183 const struct pad_conf_entry wkup_padconf_array_non_essential[] = { 184 {PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */ 185 {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ 186 {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ 187 {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */ 188 {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ 189 {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ 190 {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ 191 {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ 192 {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ 193 {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ 194 {PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */ 195 {PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */ 196 }; 197 198 199 #endif /* _DUOVERO_MUX_DATA_H_ */ 200