1 /* 2 * (C) Copyright 2013 3 * Gumstix Inc. <www.gumstix.com> 4 * Maintainer: Ash Charles <ash@gumstix.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 #include <common.h> 9 #include <netdev.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/mmc_host_def.h> 12 #include <twl6030.h> 13 #include <asm/emif.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/gpio.h> 17 #include <asm/mach-types.h> 18 19 #include "duovero_mux_data.h" 20 21 #define WIFI_EN 43 22 23 #if defined(CONFIG_CMD_NET) 24 #define SMSC_NRESET 45 25 static void setup_net_chip(void); 26 #endif 27 28 #ifdef CONFIG_USB_EHCI_HCD 29 #include <usb.h> 30 #include <asm/arch/ehci.h> 31 #include <asm/ehci-omap.h> 32 #endif 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 const struct omap_sysinfo sysinfo = { 37 "Board: duovero\n" 38 }; 39 40 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; 41 42 /** 43 * @brief board_init 44 * 45 * @return 0 46 */ 47 int board_init(void) 48 { 49 gpmc_init(); 50 51 gd->bd->bi_arch_number = MACH_TYPE_DUOVERO; 52 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 53 54 return 0; 55 } 56 57 /** 58 * @brief misc_init_r - Configure board specific configurations 59 * such as power configurations, ethernet initialization as phase2 of 60 * boot sequence 61 * 62 * @return 0 63 */ 64 int misc_init_r(void) 65 { 66 int ret = 0; 67 u8 val; 68 69 /* wifi setup: first enable 32Khz clock from 6030 pmic */ 70 val = 0xe1; 71 ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1); 72 if (ret) 73 printf("Failed to enable 32Khz clock to wifi module\n"); 74 75 /* then setup WIFI_EN as an output pin and send reset pulse */ 76 if (!gpio_request(WIFI_EN, "")) { 77 gpio_direction_output(WIFI_EN, 0); 78 gpio_set_value(WIFI_EN, 1); 79 udelay(1); 80 gpio_set_value(WIFI_EN, 0); 81 udelay(1); 82 gpio_set_value(WIFI_EN, 1); 83 } 84 85 #if defined(CONFIG_CMD_NET) 86 setup_net_chip(); 87 #endif 88 return 0; 89 } 90 91 void set_muxconf_regs(void) 92 { 93 do_set_mux((*ctrl)->control_padconf_core_base, 94 core_padconf_array_essential, 95 sizeof(core_padconf_array_essential) / 96 sizeof(struct pad_conf_entry)); 97 98 do_set_mux((*ctrl)->control_padconf_wkup_base, 99 wkup_padconf_array_essential, 100 sizeof(wkup_padconf_array_essential) / 101 sizeof(struct pad_conf_entry)); 102 103 do_set_mux((*ctrl)->control_padconf_core_base, 104 core_padconf_array_non_essential, 105 sizeof(core_padconf_array_non_essential) / 106 sizeof(struct pad_conf_entry)); 107 108 do_set_mux((*ctrl)->control_padconf_wkup_base, 109 wkup_padconf_array_non_essential, 110 sizeof(wkup_padconf_array_non_essential) / 111 sizeof(struct pad_conf_entry)); 112 } 113 114 #if defined(CONFIG_MMC) 115 int board_mmc_init(bd_t *bis) 116 { 117 return omap_mmc_init(0, 0, 0, -1, -1); 118 } 119 120 #if !defined(CONFIG_SPL_BUILD) 121 void board_mmc_power_init(void) 122 { 123 twl6030_power_mmc_init(0); 124 } 125 #endif 126 #endif 127 128 #if defined(CONFIG_CMD_NET) 129 130 #define GPMC_SIZE_16M 0xF 131 #define GPMC_BASEADDR_MASK 0x3F 132 #define GPMC_CS_ENABLE 0x1 133 134 static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs, 135 u32 base, u32 size) 136 { 137 writel(0, &cs->config7); 138 sdelay(1000); 139 /* Delay for settling */ 140 writel(gpmc_config[0], &cs->config1); 141 writel(gpmc_config[1], &cs->config2); 142 writel(gpmc_config[2], &cs->config3); 143 writel(gpmc_config[3], &cs->config4); 144 writel(gpmc_config[4], &cs->config5); 145 writel(gpmc_config[5], &cs->config6); 146 147 /* 148 * Enable the config. size is the CS size and goes in 149 * bits 11:8. We set bit 6 to enable this CS and the base 150 * address goes into bits 5:0. 151 */ 152 writel((size << 8) | (GPMC_CS_ENABLE << 6) | 153 ((base >> 24) & GPMC_BASEADDR_MASK), 154 &cs->config7); 155 156 sdelay(2000); 157 } 158 159 /* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ 160 #define NET_LAN9221_GPMC_CONFIG1 0x2a001203 161 #define NET_LAN9221_GPMC_CONFIG2 0x000a0a02 162 #define NET_LAN9221_GPMC_CONFIG3 0x00020200 163 #define NET_LAN9221_GPMC_CONFIG4 0x0a030a03 164 #define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a 165 #define NET_LAN9221_GPMC_CONFIG6 0x8a070707 166 #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c 167 168 /* GPMC definitions for LAN9221 chips on expansion boards */ 169 static const u32 gpmc_lan_config[] = { 170 NET_LAN9221_GPMC_CONFIG1, 171 NET_LAN9221_GPMC_CONFIG2, 172 NET_LAN9221_GPMC_CONFIG3, 173 NET_LAN9221_GPMC_CONFIG4, 174 NET_LAN9221_GPMC_CONFIG5, 175 NET_LAN9221_GPMC_CONFIG6, 176 /*CONFIG7- computed as params */ 177 }; 178 179 /* 180 * Routine: setup_net_chip 181 * Description: Setting up the configuration GPMC registers specific to the 182 * Ethernet hardware. 183 */ 184 static void setup_net_chip(void) 185 { 186 enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 187 GPMC_SIZE_16M); 188 189 /* Make GPIO SMSC_NRESET as output pin and send reset pulse */ 190 if (!gpio_request(SMSC_NRESET, "")) { 191 gpio_direction_output(SMSC_NRESET, 0); 192 gpio_set_value(SMSC_NRESET, 1); 193 udelay(1); 194 gpio_set_value(SMSC_NRESET, 0); 195 udelay(1); 196 gpio_set_value(SMSC_NRESET, 1); 197 } 198 } 199 #endif 200 201 int board_eth_init(bd_t *bis) 202 { 203 int rc = 0; 204 #ifdef CONFIG_SMC911X 205 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 206 #endif 207 return rc; 208 } 209 210 #ifdef CONFIG_USB_EHCI_HCD 211 212 static struct omap_usbhs_board_data usbhs_bdata = { 213 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 214 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, 215 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, 216 }; 217 218 int ehci_hcd_init(int index, enum usb_init_type init, 219 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 220 { 221 int ret; 222 unsigned int utmi_clk; 223 u32 auxclk, altclksrc; 224 225 /* Now we can enable our port clocks */ 226 utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); 227 utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; 228 setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk); 229 230 auxclk = readl(&scrm->auxclk3); 231 /* Select sys_clk */ 232 auxclk &= ~AUXCLK_SRCSELECT_MASK; 233 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; 234 /* Set the divisor to 2 */ 235 auxclk &= ~AUXCLK_CLKDIV_MASK; 236 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; 237 /* Request auxilary clock #3 */ 238 auxclk |= AUXCLK_ENABLE_MASK; 239 writel(auxclk, &scrm->auxclk3); 240 241 altclksrc = readl(&scrm->altclksrc); 242 243 /* Activate alternate system clock supplier */ 244 altclksrc &= ~ALTCLKSRC_MODE_MASK; 245 altclksrc |= ALTCLKSRC_MODE_ACTIVE; 246 247 /* enable clocks */ 248 altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; 249 250 writel(altclksrc, &scrm->altclksrc); 251 252 ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); 253 if (ret < 0) 254 return ret; 255 256 return 0; 257 } 258 259 int ehci_hcd_stop(int index) 260 { 261 return omap_ehci_hcd_stop(); 262 } 263 #endif 264 265 /* 266 * get_board_rev() - get board revision 267 */ 268 u32 get_board_rev(void) 269 { 270 return 0x20; 271 } 272