1 /* 2 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 3 * Copyright (C) 2017, Grinn - http://grinn-global.com/ 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/arch/chilisom.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/omap.h> 13 #include <asm/arch/mem.h> 14 #include <asm/arch/mmc_host_def.h> 15 #include <asm/arch/mux.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/emif.h> 18 #include <asm/io.h> 19 #include <cpsw.h> 20 #include <environment.h> 21 #include <errno.h> 22 #include <miiphy.h> 23 #include <serial.h> 24 #include <spl.h> 25 #include <watchdog.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 static __maybe_unused struct ctrl_dev *cdev = 30 (struct ctrl_dev *)CTRL_DEVICE_BASE; 31 32 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 33 static struct module_pin_mux uart0_pin_mux[] = { 34 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 35 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 36 {-1}, 37 }; 38 39 static struct module_pin_mux mmc0_pin_mux[] = { 40 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 41 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 42 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 43 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 44 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 45 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 46 {-1}, 47 }; 48 49 static struct module_pin_mux rmii1_pin_mux[] = { 50 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ 51 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ 52 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ 53 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ 54 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ 55 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ 56 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ 57 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 58 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 59 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ 60 {-1}, 61 }; 62 63 static void enable_board_pin_mux(void) 64 { 65 chilisom_enable_pin_mux(); 66 67 /* chiliboard pinmux */ 68 configure_module_pin_mux(rmii1_pin_mux); 69 configure_module_pin_mux(mmc0_pin_mux); 70 } 71 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 72 73 #ifndef CONFIG_DM_SERIAL 74 struct serial_device *default_serial_console(void) 75 { 76 return &eserial1_device; 77 } 78 #endif 79 80 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 81 void set_uart_mux_conf(void) 82 { 83 configure_module_pin_mux(uart0_pin_mux); 84 } 85 86 void set_mux_conf_regs(void) 87 { 88 enable_board_pin_mux(); 89 } 90 91 void am33xx_spl_board_init(void) 92 { 93 chilisom_spl_board_init(); 94 } 95 #endif 96 97 /* 98 * Basic board specific setup. Pinmux has been handled already. 99 */ 100 int board_init(void) 101 { 102 #if defined(CONFIG_HW_WATCHDOG) 103 hw_watchdog_init(); 104 #endif 105 106 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 107 gpmc_init(); 108 109 return 0; 110 } 111 112 #ifdef CONFIG_BOARD_LATE_INIT 113 int board_late_init(void) 114 { 115 #if !defined(CONFIG_SPL_BUILD) 116 uint8_t mac_addr[6]; 117 uint32_t mac_hi, mac_lo; 118 119 /* try reading mac address from efuse */ 120 mac_lo = readl(&cdev->macid0l); 121 mac_hi = readl(&cdev->macid0h); 122 mac_addr[0] = mac_hi & 0xFF; 123 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 124 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 125 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 126 mac_addr[4] = mac_lo & 0xFF; 127 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 128 129 if (!getenv("ethaddr")) { 130 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 131 132 if (is_valid_ethaddr(mac_addr)) 133 eth_setenv_enetaddr("ethaddr", mac_addr); 134 } 135 136 mac_lo = readl(&cdev->macid1l); 137 mac_hi = readl(&cdev->macid1h); 138 mac_addr[0] = mac_hi & 0xFF; 139 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 140 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 141 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 142 mac_addr[4] = mac_lo & 0xFF; 143 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 144 145 if (!getenv("eth1addr")) { 146 if (is_valid_ethaddr(mac_addr)) 147 eth_setenv_enetaddr("eth1addr", mac_addr); 148 } 149 #endif 150 151 return 0; 152 } 153 #endif 154 155 #if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \ 156 !defined(CONFIG_SPL_BUILD) 157 static void cpsw_control(int enabled) 158 { 159 /* VTP can be added here */ 160 161 return; 162 } 163 164 static struct cpsw_slave_data cpsw_slaves[] = { 165 { 166 .slave_reg_ofs = 0x208, 167 .sliver_reg_ofs = 0xd80, 168 .phy_addr = 0, 169 } 170 }; 171 172 static struct cpsw_platform_data cpsw_data = { 173 .mdio_base = CPSW_MDIO_BASE, 174 .cpsw_base = CPSW_BASE, 175 .mdio_div = 0xff, 176 .channels = 8, 177 .cpdma_reg_ofs = 0x800, 178 .slaves = 1, 179 .slave_data = cpsw_slaves, 180 .ale_reg_ofs = 0xd00, 181 .ale_entries = 1024, 182 .host_port_reg_ofs = 0x108, 183 .hw_stats_reg_ofs = 0x900, 184 .bd_ram_ofs = 0x2000, 185 .mac_control = (1 << 5), 186 .control = cpsw_control, 187 .host_port_num = 0, 188 .version = CPSW_CTRL_VERSION_2, 189 }; 190 191 int board_eth_init(bd_t *bis) 192 { 193 int rv, n = 0; 194 195 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 196 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 197 198 rv = cpsw_register(&cpsw_data); 199 if (rv < 0) 200 printf("Error %d registering CPSW switch\n", rv); 201 else 202 n += rv; 203 204 return n; 205 } 206 #endif 207