1*6b0071c1SPeter Senna Tschudin /* 2*6b0071c1SPeter Senna Tschudin * (C) Copyright 2015 General Electric Company 3*6b0071c1SPeter Senna Tschudin * 4*6b0071c1SPeter Senna Tschudin * SPDX-License-Identifier: GPL-2.0+ 5*6b0071c1SPeter Senna Tschudin */ 6*6b0071c1SPeter Senna Tschudin 7*6b0071c1SPeter Senna Tschudin #ifndef __PPD_GPIO_H_ 8*6b0071c1SPeter Senna Tschudin #define __PPD_GPIO_H_ 9*6b0071c1SPeter Senna Tschudin 10*6b0071c1SPeter Senna Tschudin #include <asm/arch/iomux-mx53.h> 11*6b0071c1SPeter Senna Tschudin #include <asm/gpio.h> 12*6b0071c1SPeter Senna Tschudin 13*6b0071c1SPeter Senna Tschudin #define PPD_UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 14*6b0071c1SPeter Senna Tschudin PAD_CTL_PUS_100K_UP) 15*6b0071c1SPeter Senna Tschudin 16*6b0071c1SPeter Senna Tschudin static const iomux_v3_cfg_t ppd_pads[] = { 17*6b0071c1SPeter Senna Tschudin /* FEC */ 18*6b0071c1SPeter Senna Tschudin MX53_PAD_EIM_A22__GPIO2_16, 19*6b0071c1SPeter Senna Tschudin /* UART */ 20*6b0071c1SPeter Senna Tschudin NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, PPD_UART_PAD_CTRL), 21*6b0071c1SPeter Senna Tschudin NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, PPD_UART_PAD_CTRL), 22*6b0071c1SPeter Senna Tschudin /* Video */ 23*6b0071c1SPeter Senna Tschudin MX53_PAD_CSI0_DATA_EN__GPIO5_20, /* LR_SCAN_CTRL */ 24*6b0071c1SPeter Senna Tschudin MX53_PAD_CSI0_VSYNC__GPIO5_21, /* UD_SCAN_CTRL */ 25*6b0071c1SPeter Senna Tschudin MX53_PAD_CSI0_DAT10__GPIO5_28, /* DATA_WIDTH_CTRL */ 26*6b0071c1SPeter Senna Tschudin MX53_PAD_CSI0_PIXCLK__GPIO5_18, /* HOST_CONTROLLED_RESET_TO_LCD_N */ 27*6b0071c1SPeter Senna Tschudin MX53_PAD_EIM_DA2__GPIO3_2, /* LVDS1_MUX_CTRL */ 28*6b0071c1SPeter Senna Tschudin MX53_PAD_EIM_DA3__GPIO3_3, /* LVDS0_MUX_CTRL */ 29*6b0071c1SPeter Senna Tschudin MX53_PAD_EIM_A21__GPIO2_17, /* ENABLE_PWR_TO_LCD_AND_UI_INTERFACE */ 30*6b0071c1SPeter Senna Tschudin MX53_PAD_CSI0_DAT11__GPIO5_29, /* BACKLIGHT_ENABLE */ 31*6b0071c1SPeter Senna Tschudin MX53_PAD_DISP0_DAT9__PWM2_PWMO, /* IMX535_PWM2_TO_LCD_CONNECTOR */ 32*6b0071c1SPeter Senna Tschudin /* I2C */ 33*6b0071c1SPeter Senna Tschudin MX53_PAD_EIM_A20__GPIO2_18, /* RESET_I2C1_BUS_SEGMENT_MUX_N */ 34*6b0071c1SPeter Senna Tschudin 35*6b0071c1SPeter Senna Tschudin /* SPI */ 36*6b0071c1SPeter Senna Tschudin MX53_PAD_DISP0_DAT23__GPIO5_17, 37*6b0071c1SPeter Senna Tschudin MX53_PAD_KEY_COL2__GPIO4_10, 38*6b0071c1SPeter Senna Tschudin MX53_PAD_KEY_ROW2__GPIO4_11, 39*6b0071c1SPeter Senna Tschudin MX53_PAD_KEY_COL3__GPIO4_12, 40*6b0071c1SPeter Senna Tschudin }; 41*6b0071c1SPeter Senna Tschudin 42*6b0071c1SPeter Senna Tschudin struct gpio_cfg { 43*6b0071c1SPeter Senna Tschudin unsigned int gpio; 44*6b0071c1SPeter Senna Tschudin int value; 45*6b0071c1SPeter Senna Tschudin }; 46*6b0071c1SPeter Senna Tschudin 47*6b0071c1SPeter Senna Tschudin #define RESET_IMX535_ETHERNET_PHY_N IMX_GPIO_NR(2, 16) 48*6b0071c1SPeter Senna Tschudin #define UD_SCAN_CTRL IMX_GPIO_NR(5, 21) 49*6b0071c1SPeter Senna Tschudin #define LR_SCAN_CTRL IMX_GPIO_NR(5, 20) 50*6b0071c1SPeter Senna Tschudin #define LVDS0_MUX_CTRL IMX_GPIO_NR(3, 3) 51*6b0071c1SPeter Senna Tschudin #define LVDS1_MUX_CTRL IMX_GPIO_NR(3, 2) 52*6b0071c1SPeter Senna Tschudin #define HOST_CONTROLLED_RESET_TO_LCD_N IMX_GPIO_NR(5, 18) 53*6b0071c1SPeter Senna Tschudin #define DATA_WIDTH_CTRL IMX_GPIO_NR(5, 28) 54*6b0071c1SPeter Senna Tschudin #define RESET_DP0_TRANSMITTER_N IMX_GPIO_NR(2, 28) 55*6b0071c1SPeter Senna Tschudin #define RESET_DP1_TRANSMITTER_N IMX_GPIO_NR(2, 29) 56*6b0071c1SPeter Senna Tschudin #define POWER_DOWN_LVDS0_DESERIALIZER_N IMX_GPIO_NR(2, 22) 57*6b0071c1SPeter Senna Tschudin #define POWER_DOWN_LVDS1_DESERIALIZER_N IMX_GPIO_NR(2, 27) 58*6b0071c1SPeter Senna Tschudin #define ENABLE_PWR_TO_LCD_AND_UI_INTERFACE IMX_GPIO_NR(2, 17) 59*6b0071c1SPeter Senna Tschudin #define BACKLIGHT_ENABLE IMX_GPIO_NR(5, 29) 60*6b0071c1SPeter Senna Tschudin #define RESET_I2C1_BUS_SEGMENT_MUX_N IMX_GPIO_NR(2, 18) 61*6b0071c1SPeter Senna Tschudin #define ECSPI1_CS0 IMX_GPIO_NR(5, 17) 62*6b0071c1SPeter Senna Tschudin #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) 63*6b0071c1SPeter Senna Tschudin #define ECSPI1_CS2 IMX_GPIO_NR(4, 11) 64*6b0071c1SPeter Senna Tschudin #define ECSPI1_CS3 IMX_GPIO_NR(4, 12) 65*6b0071c1SPeter Senna Tschudin 66*6b0071c1SPeter Senna Tschudin static const struct gpio_cfg ppd_gpios[] = { 67*6b0071c1SPeter Senna Tschudin /* FEC */ 68*6b0071c1SPeter Senna Tschudin /* Drive Low as GPIO output for 25ms per Eth Phy IX spec */ 69*6b0071c1SPeter Senna Tschudin /* Then Drive High as GPIO output to bring Eth Phy IC out of reset */ 70*6b0071c1SPeter Senna Tschudin { RESET_IMX535_ETHERNET_PHY_N, 0 }, 71*6b0071c1SPeter Senna Tschudin { RESET_IMX535_ETHERNET_PHY_N, 1 }, 72*6b0071c1SPeter Senna Tschudin /* Video */ 73*6b0071c1SPeter Senna Tschudin { UD_SCAN_CTRL, 0 }, 74*6b0071c1SPeter Senna Tschudin { LR_SCAN_CTRL, 1 }, 75*6b0071c1SPeter Senna Tschudin #ifdef PROPRIETARY_CHANGES 76*6b0071c1SPeter Senna Tschudin { LVDS0_MUX_CTRL, 1 }, 77*6b0071c1SPeter Senna Tschudin #else 78*6b0071c1SPeter Senna Tschudin { LVDS0_MUX_CTRL, 0 }, 79*6b0071c1SPeter Senna Tschudin #endif 80*6b0071c1SPeter Senna Tschudin { LVDS1_MUX_CTRL, 1 }, 81*6b0071c1SPeter Senna Tschudin { HOST_CONTROLLED_RESET_TO_LCD_N, 1 }, 82*6b0071c1SPeter Senna Tschudin { DATA_WIDTH_CTRL, 0 }, 83*6b0071c1SPeter Senna Tschudin { RESET_DP0_TRANSMITTER_N, 1 }, 84*6b0071c1SPeter Senna Tschudin { RESET_DP1_TRANSMITTER_N, 1 }, 85*6b0071c1SPeter Senna Tschudin { POWER_DOWN_LVDS0_DESERIALIZER_N, 1 }, 86*6b0071c1SPeter Senna Tschudin { POWER_DOWN_LVDS1_DESERIALIZER_N, 1 }, 87*6b0071c1SPeter Senna Tschudin { ENABLE_PWR_TO_LCD_AND_UI_INTERFACE, 1 }, 88*6b0071c1SPeter Senna Tschudin { BACKLIGHT_ENABLE, 0 }, 89*6b0071c1SPeter Senna Tschudin { RESET_I2C1_BUS_SEGMENT_MUX_N, 1 }, 90*6b0071c1SPeter Senna Tschudin { ECSPI1_CS0, 1 }, 91*6b0071c1SPeter Senna Tschudin { ECSPI1_CS1, 1 }, 92*6b0071c1SPeter Senna Tschudin { ECSPI1_CS2, 1 }, 93*6b0071c1SPeter Senna Tschudin { ECSPI1_CS3, 1 }, 94*6b0071c1SPeter Senna Tschudin }; 95*6b0071c1SPeter Senna Tschudin 96*6b0071c1SPeter Senna Tschudin #endif /* __PPD_GPIO_H_ */ 97