1 /*
2  * Copyright 2017 General Electric Company
3  *
4  * Based on board/freescale/mx53loco/mx53loco_video.c:
5  *
6  * Copyright (C) 2012 Freescale Semiconductor, Inc.
7  * Fabio Estevam <fabio.estevam@freescale.com>
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <common.h>
13 #include <linux/list.h>
14 #include <asm/gpio.h>
15 #include <asm/arch/iomux-mx53.h>
16 #include <linux/fb.h>
17 #include <ipu_pixfmt.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/io.h>
21 #include <pwm.h>
22 #include "ppd_gpio.h"
23 
24 #define MX53PPD_LCD_POWER		IMX_GPIO_NR(3, 24)
25 
26 static struct fb_videomode const nv_spwg = {
27 	.name		= "NV-SPWGRGB888",
28 	.refresh	= 60,
29 	.xres		= 800,
30 	.yres		= 480,
31 	.pixclock	= 15384,
32 	.left_margin	= 16,
33 	.right_margin	= 210,
34 	.upper_margin	= 10,
35 	.lower_margin	= 22,
36 	.hsync_len	= 30,
37 	.vsync_len	= 13,
38 	.sync		= FB_SYNC_EXT,
39 	.vmode		= FB_VMODE_NONINTERLACED
40 };
41 
42 void setup_iomux_lcd(void)
43 {
44 	static const iomux_v3_cfg_t lcd_pads[] = {
45 		MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
46 		MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
47 		MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
48 		MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
49 		MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
50 		MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
51 		MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
52 		MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
53 		MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
54 		MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
55 		MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
56 		MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
57 		MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
58 		MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
59 		MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
60 		MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
61 		MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
62 		MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
63 		MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
64 		MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
65 		MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
66 		MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
67 		MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
68 		MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
69 		MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
70 		MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
71 		MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
72 		MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
73 	};
74 
75 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
76 }
77 
78 static void lcd_enable(void)
79 {
80 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
81 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
82 
83 	/* Set LDB_DI0 as clock source for IPU_DI0 */
84 	clrsetbits_le32(&mxc_ccm->cscmr2,
85 			MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK,
86 			MXC_CCM_CSCMR2_DI0_CLK_SEL(
87 				MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK));
88 
89 	/* Turn on IPU LDB DI0 clocks */
90 	setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_LDB_DI0(3));
91 
92 	/* Turn on IPU DI0 clocks */
93 	setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_IPU_DI0(3));
94 
95 	/* Configure LDB */
96 	writel(IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
97 		IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
98 		IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
99 		&iomux->gpr[2]);
100 
101 	/* Enable backlights  */
102 	pwm_init(1, 0, 0);
103 
104 	/* duty cycle 5000000ns, period: 5000000ns */
105 	pwm_config(1, 5000000, 5000000);
106 
107 	/* Backlight Power */
108 	gpio_direction_output(BACKLIGHT_ENABLE, 1);
109 
110 	pwm_enable(1);
111 }
112 
113 static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc,
114 			 char * const argv[])
115 {
116 	lcd_enable();
117 	return 0;
118 }
119 
120 U_BOOT_CMD(
121 	ppd_lcd_enable,	1,	1,	do_lcd_enable,
122 	"enable PPD LCD",
123 	"no parameters"
124 );
125 
126 int board_video_skip(void)
127 {
128 	int ret;
129 
130 	ret = ipuv3_fb_init(&nv_spwg, 0, IPU_PIX_FMT_RGB24);
131 	if (ret)
132 		printf("Display cannot be configured: %d\n", ret);
133 
134 	return ret;
135 }
136