1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * 4 * Copyright 2015 Timesys Corporation. 5 * Copyright 2015 General Electric Company 6 * 7 * Refer doc/README.imximage for more details about how-to configure 8 * and create imximage boot image 9 * 10 * The syntax is taken as close as possible with the kwbimage 11 */ 12 13IMAGE_VERSION 2 14BOOT_FROM sd 15 16#define __ASSEMBLY__ 17#include <config.h> 18#include "asm/arch/mx6-ddr.h" 19#include "asm/arch/iomux.h" 20#include "asm/arch/crm_regs.h" 21 22/* DDR IO */ 23DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 24DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 25DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 26DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 27DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 28DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 29DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 30DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 31DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 32DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 33DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 34DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 35DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 36DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 37DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 38DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 39DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 40DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 41DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 42DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 43DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 44DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 45DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 46DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 47DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 48DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 49DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 50DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 51DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 52DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 53DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 54DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 55DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 56DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 57DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 58DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 59DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 60DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 61 62/* Calibrations */ 63/* ZQ */ 64DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 65/* write leveling */ 66DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 67DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 68DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F 69DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 70/* Read DQS Gating calibration */ 71DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544 72DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530 73DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C 74DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C 75/* Read calibration */ 76DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032 77DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042 78/* Write calibration */ 79DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E 80DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E 81/* read data bit delay */ 82DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 83DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 84DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 85DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 86DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 87DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 88DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 89DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 90 91/* Complete calibration by forced measurment */ 92DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 93DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 94 95/* MMDC init */ 96DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 97DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 98DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4 99DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 100DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db 101DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 102DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 103DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 104DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023 105DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 106DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000 107 108/* Initialize Micron MT41J128M */ 109DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 110DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a 111DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 112DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b 113DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031 114DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039 115DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 116DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 117DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 118DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 119DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 120DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 121DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 122DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 123DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 124DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 125 126/* set the default clock gate to save power */ 127DATA 4, CCM_CCGR0, 0x00C03F3F 128DATA 4, CCM_CCGR1, 0x0030FC03 129DATA 4, CCM_CCGR2, 0x0FFFC000 130DATA 4, CCM_CCGR3, 0x3FF00000 131DATA 4, CCM_CCGR4, 0x00FFF300 132DATA 4, CCM_CCGR5, 0x0F0000C3 133DATA 4, CCM_CCGR6, 0x000003FF 134 135/* enable AXI cache for VDOA/VPU/IPU */ 136DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 137/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 138DATA 4, MX6_IOMUXC_GPR6, 0x007F007F 139DATA 4, MX6_IOMUXC_GPR7, 0x007F007F 140 141/* 142 * Setup CCM_CCOSR register as follows: 143 * 144 * cko1_en 1 --> CKO1 enabled 145 * cko1_div 111 --> divide by 8 146 * cko1_sel 1011 --> ahb_clk_root 147 * 148 * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz 149 */ 150DATA 4, CCM_CCOSR, 0x000000fb 151