1/* 2 * 3 * Copyright 2015 Timesys Corporation. 4 * Copyright 2015 General Electric Company 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * Refer doc/README.imximage for more details about how-to configure 9 * and create imximage boot image 10 * 11 * The syntax is taken as close as possible with the kwbimage 12 */ 13 14IMAGE_VERSION 2 15BOOT_FROM sd 16 17#define __ASSEMBLY__ 18#include <config.h> 19#include "asm/arch/mx6-ddr.h" 20#include "asm/arch/iomux.h" 21#include "asm/arch/crm_regs.h" 22 23/* DDR IO */ 24DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 25DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 26DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 27DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 28DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 29DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 30DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 31DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 32DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 33DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 34DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 35DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 36DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 37DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 38DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 39DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 40DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 41DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 42DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 43DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 44DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 45DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 46DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 47DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 48DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 49DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 50DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 51DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 52DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 53DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 54DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 55DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 56DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 57DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 58DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 59DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 60DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 61DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 62 63/* Calibrations */ 64/* ZQ */ 65DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 66/* write leveling */ 67DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 68DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 69DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F 70DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 71/* Read DQS Gating calibration */ 72DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544 73DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530 74DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C 75DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C 76/* Read calibration */ 77DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032 78DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042 79/* Write calibration */ 80DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E 81DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E 82/* read data bit delay */ 83DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 84DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 85DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 86DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 87DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 88DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 89DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 90DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 91 92/* Complete calibration by forced measurment */ 93DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 94DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 95 96/* MMDC init */ 97DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 98DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 99DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4 100DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 101DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db 102DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 103DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 104DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 105DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023 106DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 107DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000 108 109/* Initialize Micron MT41J128M */ 110DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 111DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a 112DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 113DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b 114DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031 115DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039 116DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 117DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 118DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 119DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 120DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 121DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 122DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 123DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 124DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 125DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 126 127/* set the default clock gate to save power */ 128DATA 4, CCM_CCGR0, 0x00C03F3F 129DATA 4, CCM_CCGR1, 0x0030FC03 130DATA 4, CCM_CCGR2, 0x0FFFC000 131DATA 4, CCM_CCGR3, 0x3FF00000 132DATA 4, CCM_CCGR4, 0x00FFF300 133DATA 4, CCM_CCGR5, 0x0F0000C3 134DATA 4, CCM_CCGR6, 0x000003FF 135 136/* enable AXI cache for VDOA/VPU/IPU */ 137DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 138/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 139DATA 4, MX6_IOMUXC_GPR6, 0x007F007F 140DATA 4, MX6_IOMUXC_GPR7, 0x007F007F 141 142/* 143 * Setup CCM_CCOSR register as follows: 144 * 145 * cko1_en 1 --> CKO1 enabled 146 * cko1_div 111 --> divide by 8 147 * cko1_sel 1011 --> ahb_clk_root 148 * 149 * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz 150 */ 151DATA 4, CCM_CCOSR, 0x000000fb 152