1 /* 2 * Copyright 2015 Timesys Corporation 3 * Copyright 2015 General Electric Company 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <linux/errno.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-imx/mxc_i2c.h> 16 #include <asm/mach-imx/iomux-v3.h> 17 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/video.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <miiphy.h> 22 #include <netdev.h> 23 #include <asm/arch/mxc_hdmi.h> 24 #include <asm/arch/crm_regs.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <i2c.h> 28 #include <pwm.h> 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 32 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 33 PAD_CTL_HYS) 34 35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 44 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 45 46 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ 47 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) 48 49 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 50 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 51 52 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 53 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 54 55 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 57 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 58 59 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 60 61 int dram_init(void) 62 { 63 gd->ram_size = imx_ddr_size(); 64 65 return 0; 66 } 67 68 static iomux_v3_cfg_t const uart3_pads[] = { 69 MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 70 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 71 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 72 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 73 }; 74 75 static iomux_v3_cfg_t const uart4_pads[] = { 76 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 77 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 78 }; 79 80 static iomux_v3_cfg_t const enet_pads[] = { 81 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 87 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 88 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 89 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 90 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 91 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 92 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 93 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 94 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 95 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 96 /* AR8033 PHY Reset */ 97 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 98 }; 99 100 static void setup_iomux_enet(void) 101 { 102 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 103 104 /* Reset AR8033 PHY */ 105 gpio_direction_output(IMX_GPIO_NR(1, 28), 0); 106 mdelay(10); 107 gpio_set_value(IMX_GPIO_NR(1, 28), 1); 108 mdelay(1); 109 } 110 111 static iomux_v3_cfg_t const usdhc2_pads[] = { 112 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 115 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 119 }; 120 121 static iomux_v3_cfg_t const usdhc3_pads[] = { 122 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 124 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 126 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 127 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 128 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 }; 134 135 static iomux_v3_cfg_t const usdhc4_pads[] = { 136 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 137 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 138 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 139 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 140 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 141 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 142 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 143 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 144 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 145 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 146 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 147 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 148 }; 149 150 static iomux_v3_cfg_t const ecspi1_pads[] = { 151 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 152 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 153 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 154 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), 155 }; 156 157 static struct i2c_pads_info i2c_pad_info1 = { 158 .scl = { 159 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD, 160 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD, 161 .gp = IMX_GPIO_NR(5, 27) 162 }, 163 .sda = { 164 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD, 165 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD, 166 .gp = IMX_GPIO_NR(5, 26) 167 } 168 }; 169 170 static struct i2c_pads_info i2c_pad_info2 = { 171 .scl = { 172 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, 173 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, 174 .gp = IMX_GPIO_NR(4, 12) 175 }, 176 .sda = { 177 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, 178 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, 179 .gp = IMX_GPIO_NR(4, 13) 180 } 181 }; 182 183 static struct i2c_pads_info i2c_pad_info3 = { 184 .scl = { 185 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD, 186 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD, 187 .gp = IMX_GPIO_NR(1, 3) 188 }, 189 .sda = { 190 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, 191 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, 192 .gp = IMX_GPIO_NR(1, 6) 193 } 194 }; 195 196 #ifdef CONFIG_MXC_SPI 197 int board_spi_cs_gpio(unsigned bus, unsigned cs) 198 { 199 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1; 200 } 201 202 static void setup_spi(void) 203 { 204 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); 205 } 206 #endif 207 208 static iomux_v3_cfg_t const pcie_pads[] = { 209 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), 210 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 211 }; 212 213 static void setup_pcie(void) 214 { 215 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 216 } 217 218 static void setup_iomux_uart(void) 219 { 220 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 221 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 222 } 223 224 #ifdef CONFIG_FSL_ESDHC 225 struct fsl_esdhc_cfg usdhc_cfg[3] = { 226 {USDHC2_BASE_ADDR}, 227 {USDHC3_BASE_ADDR}, 228 {USDHC4_BASE_ADDR}, 229 }; 230 231 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 232 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11) 233 234 int board_mmc_getcd(struct mmc *mmc) 235 { 236 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 237 int ret = 0; 238 239 switch (cfg->esdhc_base) { 240 case USDHC2_BASE_ADDR: 241 ret = !gpio_get_value(USDHC2_CD_GPIO); 242 break; 243 case USDHC3_BASE_ADDR: 244 ret = 1; /* eMMC is always present */ 245 break; 246 case USDHC4_BASE_ADDR: 247 ret = !gpio_get_value(USDHC4_CD_GPIO); 248 break; 249 } 250 251 return ret; 252 } 253 254 int board_mmc_init(bd_t *bis) 255 { 256 int ret; 257 int i; 258 259 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 260 switch (i) { 261 case 0: 262 imx_iomux_v3_setup_multiple_pads( 263 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 264 gpio_direction_input(USDHC2_CD_GPIO); 265 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 266 break; 267 case 1: 268 imx_iomux_v3_setup_multiple_pads( 269 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 270 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 271 break; 272 case 2: 273 imx_iomux_v3_setup_multiple_pads( 274 usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); 275 gpio_direction_input(USDHC4_CD_GPIO); 276 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); 277 break; 278 default: 279 printf("Warning: you configured more USDHC controllers\n" 280 "(%d) then supported by the board (%d)\n", 281 i + 1, CONFIG_SYS_FSL_USDHC_NUM); 282 return -EINVAL; 283 } 284 285 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 286 if (ret) 287 return ret; 288 } 289 290 return 0; 291 } 292 #endif 293 294 static int mx6_rgmii_rework(struct phy_device *phydev) 295 { 296 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ 297 /* set device address 0x7 */ 298 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 299 /* offset 0x8016: CLK_25M Clock Select */ 300 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 301 /* enable register write, no post increment, address 0x7 */ 302 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 303 /* set to 125 MHz from local PLL source */ 304 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); 305 306 /* rgmii tx clock delay enable */ 307 /* set debug port address: SerDes Test and System Mode Control */ 308 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); 309 /* enable rgmii tx clock delay */ 310 /* set the reserved bits to avoid board specific voltage peak issue*/ 311 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); 312 313 return 0; 314 } 315 316 int board_phy_config(struct phy_device *phydev) 317 { 318 mx6_rgmii_rework(phydev); 319 320 if (phydev->drv->config) 321 phydev->drv->config(phydev); 322 323 return 0; 324 } 325 326 #if defined(CONFIG_VIDEO_IPUV3) 327 static iomux_v3_cfg_t const backlight_pads[] = { 328 /* Power for LVDS Display */ 329 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 330 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22) 331 /* Backlight enable for LVDS display */ 332 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), 333 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0) 334 /* backlight PWM brightness control */ 335 MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), 336 }; 337 338 static void do_enable_hdmi(struct display_info_t const *dev) 339 { 340 imx_enable_hdmi_phy(); 341 } 342 343 int board_cfb_skip(void) 344 { 345 gpio_direction_output(LVDS_POWER_GP, 1); 346 347 return 0; 348 } 349 350 static int detect_baseboard(struct display_info_t const *dev) 351 { 352 if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) || 353 IS_ENABLED(CONFIG_TARGET_GE_B650V3)) 354 return 1; 355 356 return 0; 357 } 358 359 struct display_info_t const displays[] = {{ 360 .bus = -1, 361 .addr = -1, 362 .pixfmt = IPU_PIX_FMT_RGB24, 363 .detect = detect_baseboard, 364 .enable = NULL, 365 .mode = { 366 .name = "G121X1-L03", 367 .refresh = 60, 368 .xres = 1024, 369 .yres = 768, 370 .pixclock = 15385, 371 .left_margin = 20, 372 .right_margin = 300, 373 .upper_margin = 30, 374 .lower_margin = 8, 375 .hsync_len = 1, 376 .vsync_len = 1, 377 .sync = FB_SYNC_EXT, 378 .vmode = FB_VMODE_NONINTERLACED 379 } }, { 380 .bus = -1, 381 .addr = 3, 382 .pixfmt = IPU_PIX_FMT_RGB24, 383 .detect = detect_hdmi, 384 .enable = do_enable_hdmi, 385 .mode = { 386 .name = "HDMI", 387 .refresh = 60, 388 .xres = 1024, 389 .yres = 768, 390 .pixclock = 15385, 391 .left_margin = 220, 392 .right_margin = 40, 393 .upper_margin = 21, 394 .lower_margin = 7, 395 .hsync_len = 60, 396 .vsync_len = 10, 397 .sync = FB_SYNC_EXT, 398 .vmode = FB_VMODE_NONINTERLACED 399 } } }; 400 size_t display_count = ARRAY_SIZE(displays); 401 402 static void enable_videopll(void) 403 { 404 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 405 s32 timeout = 100000; 406 407 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); 408 409 /* set video pll to 910MHz (24MHz * (37+11/12)) 410 * video pll post div to 910/4 = 227.5MHz 411 */ 412 clrsetbits_le32(&ccm->analog_pll_video, 413 BM_ANADIG_PLL_VIDEO_DIV_SELECT | 414 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, 415 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | 416 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0)); 417 418 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); 419 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); 420 421 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); 422 423 while (timeout--) 424 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) 425 break; 426 427 if (timeout < 0) 428 printf("Warning: video pll lock timeout!\n"); 429 430 clrsetbits_le32(&ccm->analog_pll_video, 431 BM_ANADIG_PLL_VIDEO_BYPASS, 432 BM_ANADIG_PLL_VIDEO_ENABLE); 433 } 434 435 static void setup_display_b850v3(void) 436 { 437 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 438 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 439 440 enable_videopll(); 441 442 /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */ 443 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); 444 445 imx_setup_hdmi(); 446 447 /* Set LDB_DI0 as clock source for IPU_DI0 */ 448 clrsetbits_le32(&mxc_ccm->chsccdr, 449 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, 450 (CHSCCDR_CLK_SEL_LDB_DI0 << 451 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); 452 453 /* Turn on IPU LDB DI0 clocks */ 454 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); 455 456 enable_ipu_clock(); 457 458 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | 459 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | 460 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | 461 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | 462 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | 463 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 464 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | 465 IOMUXC_GPR2_SPLIT_MODE_EN_MASK | 466 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | 467 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0, 468 &iomux->gpr[2]); 469 470 clrbits_le32(&iomux->gpr[3], 471 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | 472 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | 473 IOMUXC_GPR3_HDMI_MUX_CTL_MASK); 474 } 475 476 static void setup_display_bx50v3(void) 477 { 478 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 479 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 480 481 /* When a reset/reboot is performed the display power needs to be turned 482 * off for atleast 500ms. The boot time is ~300ms, we need to wait for 483 * an additional 200ms here. Unfortunately we use external PMIC for 484 * doing the reset, so can not differentiate between POR vs soft reset 485 */ 486 mdelay(200); 487 488 /* IPU1 DI0 clock is 480/7 = 68.5 MHz */ 489 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); 490 491 /* Set LDB_DI0 as clock source for IPU_DI0 */ 492 clrsetbits_le32(&mxc_ccm->chsccdr, 493 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, 494 (CHSCCDR_CLK_SEL_LDB_DI0 << 495 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)); 496 497 /* Turn on IPU LDB DI0 clocks */ 498 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); 499 500 enable_ipu_clock(); 501 502 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | 503 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | 504 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 505 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | 506 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, 507 &iomux->gpr[2]); 508 509 clrsetbits_le32(&iomux->gpr[3], 510 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, 511 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << 512 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); 513 514 /* backlights off until needed */ 515 imx_iomux_v3_setup_multiple_pads(backlight_pads, 516 ARRAY_SIZE(backlight_pads)); 517 gpio_direction_input(LVDS_POWER_GP); 518 gpio_direction_input(LVDS_BACKLIGHT_GP); 519 } 520 #endif /* CONFIG_VIDEO_IPUV3 */ 521 522 /* 523 * Do not overwrite the console 524 * Use always serial for U-Boot console 525 */ 526 int overwrite_console(void) 527 { 528 return 1; 529 } 530 531 int board_eth_init(bd_t *bis) 532 { 533 setup_iomux_enet(); 534 setup_pcie(); 535 536 return cpu_eth_init(bis); 537 } 538 539 static iomux_v3_cfg_t const misc_pads[] = { 540 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 541 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL), 542 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL), 543 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL), 544 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL), 545 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL), 546 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL), 547 }; 548 #define SUS_S3_OUT IMX_GPIO_NR(4, 11) 549 #define WIFI_EN IMX_GPIO_NR(6, 14) 550 551 int board_early_init_f(void) 552 { 553 imx_iomux_v3_setup_multiple_pads(misc_pads, 554 ARRAY_SIZE(misc_pads)); 555 556 setup_iomux_uart(); 557 558 #if defined(CONFIG_VIDEO_IPUV3) 559 if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) 560 /* Set LDB clock to Video PLL */ 561 select_ldb_di_clock_source(MXC_PLL5_CLK); 562 else 563 /* Set LDB clock to USB PLL */ 564 select_ldb_di_clock_source(MXC_PLL3_SW_CLK); 565 #endif 566 return 0; 567 } 568 569 int board_init(void) 570 { 571 gpio_direction_output(SUS_S3_OUT, 1); 572 gpio_direction_output(WIFI_EN, 1); 573 #if defined(CONFIG_VIDEO_IPUV3) 574 if (IS_ENABLED(CONFIG_TARGET_GE_B850V3)) 575 setup_display_b850v3(); 576 else 577 setup_display_bx50v3(); 578 #endif 579 /* address of boot parameters */ 580 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 581 582 #ifdef CONFIG_MXC_SPI 583 setup_spi(); 584 #endif 585 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 586 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 587 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); 588 589 return 0; 590 } 591 592 #ifdef CONFIG_CMD_BMODE 593 static const struct boot_mode board_boot_modes[] = { 594 /* 4 bit bus width */ 595 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 596 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 597 {NULL, 0}, 598 }; 599 #endif 600 601 void pmic_init(void) 602 { 603 #define I2C_PMIC 0x2 604 #define DA9063_I2C_ADDR 0x58 605 #define DA9063_REG_BCORE2_CFG 0x9D 606 #define DA9063_REG_BCORE1_CFG 0x9E 607 #define DA9063_REG_BPRO_CFG 0x9F 608 #define DA9063_REG_BIO_CFG 0xA0 609 #define DA9063_REG_BMEM_CFG 0xA1 610 #define DA9063_REG_BPERI_CFG 0xA2 611 #define DA9063_BUCK_MODE_MASK 0xC0 612 #define DA9063_BUCK_MODE_MANUAL 0x00 613 #define DA9063_BUCK_MODE_SLEEP 0x40 614 #define DA9063_BUCK_MODE_SYNC 0x80 615 #define DA9063_BUCK_MODE_AUTO 0xC0 616 617 uchar val; 618 619 i2c_set_bus_num(I2C_PMIC); 620 621 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1); 622 val &= ~DA9063_BUCK_MODE_MASK; 623 val |= DA9063_BUCK_MODE_SYNC; 624 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1); 625 626 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1); 627 val &= ~DA9063_BUCK_MODE_MASK; 628 val |= DA9063_BUCK_MODE_SYNC; 629 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1); 630 631 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1); 632 val &= ~DA9063_BUCK_MODE_MASK; 633 val |= DA9063_BUCK_MODE_SYNC; 634 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1); 635 636 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1); 637 val &= ~DA9063_BUCK_MODE_MASK; 638 val |= DA9063_BUCK_MODE_SYNC; 639 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1); 640 641 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1); 642 val &= ~DA9063_BUCK_MODE_MASK; 643 val |= DA9063_BUCK_MODE_SYNC; 644 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1); 645 646 i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1); 647 val &= ~DA9063_BUCK_MODE_MASK; 648 val |= DA9063_BUCK_MODE_SYNC; 649 i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1); 650 } 651 652 int board_late_init(void) 653 { 654 #ifdef CONFIG_CMD_BMODE 655 add_board_boot_modes(board_boot_modes); 656 #endif 657 658 #ifdef CONFIG_VIDEO_IPUV3 659 /* We need at least 200ms between power on and backlight on 660 * as per specifications from CHI MEI */ 661 mdelay(250); 662 663 /* enable backlight PWM 1 */ 664 pwm_init(0, 0, 0); 665 666 /* duty cycle 5000000ns, period: 5000000ns */ 667 pwm_config(0, 5000000, 5000000); 668 669 /* Backlight Power */ 670 gpio_direction_output(LVDS_BACKLIGHT_GP, 1); 671 672 pwm_enable(0); 673 #endif 674 675 /* board specific pmic init */ 676 pmic_init(); 677 678 return 0; 679 } 680 681 int checkboard(void) 682 { 683 printf("BOARD: %s\n", CONFIG_BOARD_NAME); 684 return 0; 685 } 686