1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * Authors: Timur Tabi <timur@freescale.com> 4 * 5 * FSL DIU Framebuffer driver 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <command.h> 12 #include <linux/ctype.h> 13 #include <asm/io.h> 14 #include <stdio_dev.h> 15 #include <video_fb.h> 16 #include <fsl_diu_fb.h> 17 18 #define PMUXCR_ELBCDIU_MASK 0xc0000000 19 #define PMUXCR_ELBCDIU_NOR16 0x80000000 20 #define PMUXCR_ELBCDIU_DIU 0x40000000 21 22 /* 23 * DIU Area Descriptor 24 * 25 * Note that we need to byte-swap the value before it's written to the AD 26 * register. So even though the registers don't look like they're in the same 27 * bit positions as they are on the MPC8610, the same value is written to the 28 * AD register on the MPC8610 and on the P1022. 29 */ 30 #define AD_BYTE_F 0x10000000 31 #define AD_ALPHA_C_SHIFT 25 32 #define AD_BLUE_C_SHIFT 23 33 #define AD_GREEN_C_SHIFT 21 34 #define AD_RED_C_SHIFT 19 35 #define AD_PIXEL_S_SHIFT 16 36 #define AD_COMP_3_SHIFT 12 37 #define AD_COMP_2_SHIFT 8 38 #define AD_COMP_1_SHIFT 4 39 #define AD_COMP_0_SHIFT 0 40 41 /* 42 * Variables used by the DIU/LBC switching code. It's safe to makes these 43 * global, because the DIU requires DDR, so we'll only run this code after 44 * relocation. 45 */ 46 static u32 pmuxcr; 47 48 void diu_set_pixel_clock(unsigned int pixclock) 49 { 50 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 51 unsigned long speed_ccb, temp; 52 u32 pixval; 53 54 speed_ccb = get_bus_freq(0); 55 temp = 1000000000 / pixclock; 56 temp *= 1000; 57 pixval = speed_ccb / temp; 58 debug("DIU pixval = %u\n", pixval); 59 60 /* Modify PXCLK in GUTS CLKDVDR */ 61 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; 62 out_be32(&gur->clkdvdr, temp); /* turn off clock */ 63 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); 64 } 65 66 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) 67 { 68 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 69 u32 pixel_format; 70 71 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | 72 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | 73 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | 74 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | 75 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); 76 77 printf("DIU: Switching to %ux%u\n", xres, yres); 78 79 /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ 80 clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); 81 pmuxcr = in_be32(&gur->pmuxcr); 82 83 return fsl_diu_init(xres, yres, pixel_format, 0); 84 } 85