1 /* 2 * (C) Copyright 2013 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <command.h> 26 #include <pci.h> 27 #include <asm/processor.h> 28 #include <asm/mmu.h> 29 #include <asm/cache.h> 30 #include <asm/immap_85xx.h> 31 #include <asm/fsl_pci.h> 32 #include <fsl_ddr_sdram.h> 33 #include <asm/fsl_serdes.h> 34 #include <asm/io.h> 35 #include <libfdt.h> 36 #include <fdt_support.h> 37 #include <fsl_mdio.h> 38 #include <tsec.h> 39 #include <asm/fsl_law.h> 40 #include <netdev.h> 41 #include <i2c.h> 42 #include <pca9698.h> 43 #include <watchdog.h> 44 #include "../common/dp501.h" 45 #include "controlcenterd-id.h" 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 enum { 50 HWVER_100 = 0, 51 HWVER_110 = 1, 52 HWVER_120 = 2, 53 }; 54 55 struct ihs_fpga { 56 u32 reflection_low; /* 0x0000 */ 57 u32 versions; /* 0x0004 */ 58 u32 fpga_version; /* 0x0008 */ 59 u32 fpga_features; /* 0x000c */ 60 u32 reserved[4]; /* 0x0010 */ 61 u32 control; /* 0x0020 */ 62 }; 63 64 #ifndef CONFIG_TRAILBLAZER 65 static struct pci_device_id hydra_supported[] = { 66 { 0x6d5e, 0xcdc0 }, 67 {} 68 }; 69 70 static void hydra_initialize(void); 71 #endif 72 73 int board_early_init_f(void) 74 { 75 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 76 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); 77 78 /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */ 79 clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000); 80 81 /* Set pmuxcr to allow both i2c1 and i2c2 */ 82 setbits_be32(&gur->pmuxcr, 0x00001000); 83 84 /* Set pmuxcr to enable GPIO 3_11-3_13 */ 85 setbits_be32(&gur->pmuxcr, 0x00000010); 86 87 /* Set pmuxcr to enable GPIO 2_31,3_9+10 */ 88 setbits_be32(&gur->pmuxcr, 0x00000020); 89 90 /* Set pmuxcr to enable GPIO 2_28-2_30 */ 91 setbits_be32(&gur->pmuxcr, 0x000000c0); 92 93 /* Set pmuxcr to enable GPIO 3_20-3_22 */ 94 setbits_be32(&gur->pmuxcr2, 0x03000000); 95 96 /* Set pmuxcr to enable IRQ0-2 */ 97 clrbits_be32(&gur->pmuxcr, 0x00000300); 98 99 /* Set pmuxcr to disable IRQ3-11 */ 100 setbits_be32(&gur->pmuxcr, 0x000000F0); 101 102 /* Read back the register to synchronize the write. */ 103 in_be32(&gur->pmuxcr); 104 105 /* Set the pin muxing to enable ETSEC2. */ 106 clrbits_be32(&gur->pmuxcr2, 0x001F8000); 107 108 #ifdef CONFIG_TRAILBLAZER 109 /* 110 * GPIO3_10 SPERRTRIGGER 111 */ 112 setbits_be32(&pgpio->gpdir, 0x00200000); 113 clrbits_be32(&pgpio->gpdat, 0x00200000); 114 udelay(100); 115 setbits_be32(&pgpio->gpdat, 0x00200000); 116 udelay(100); 117 clrbits_be32(&pgpio->gpdat, 0x00200000); 118 #endif 119 120 /* 121 * GPIO3_11 CPU-TO-FPGA-RESET# 122 */ 123 setbits_be32(&pgpio->gpdir, 0x00100000); 124 clrbits_be32(&pgpio->gpdat, 0x00100000); 125 126 /* 127 * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER# 128 */ 129 setbits_be32(&pgpio->gpdir, 0x00000400); 130 131 return 0; 132 } 133 134 int checkboard(void) 135 { 136 printf("Board: ControlCenter DIGITAL\n"); 137 138 return 0; 139 } 140 141 int misc_init_r(void) 142 { 143 return 0; 144 } 145 146 /* 147 * A list of PCI and SATA slots 148 */ 149 enum slot_id { 150 SLOT_PCIE1 = 1, 151 SLOT_PCIE2, 152 SLOT_PCIE3, 153 SLOT_PCIE4, 154 SLOT_PCIE5, 155 SLOT_SATA1, 156 SLOT_SATA2 157 }; 158 159 /* 160 * This array maps the slot identifiers to their names on the P1022DS board. 161 */ 162 static const char * const slot_names[] = { 163 [SLOT_PCIE1] = "Slot 1", 164 [SLOT_PCIE2] = "Slot 2", 165 [SLOT_PCIE3] = "Slot 3", 166 [SLOT_PCIE4] = "Slot 4", 167 [SLOT_PCIE5] = "Mini-PCIe", 168 [SLOT_SATA1] = "SATA 1", 169 [SLOT_SATA2] = "SATA 2", 170 }; 171 172 /* 173 * This array maps a given SERDES configuration and SERDES device to the PCI or 174 * SATA slot that it connects to. This mapping is hard-coded in the FPGA. 175 */ 176 static u8 serdes_dev_slot[][SATA2 + 1] = { 177 [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, 178 [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 179 [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, 180 [PCIE2] = SLOT_PCIE5 }, 181 [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 182 [PCIE2] = SLOT_PCIE3, 183 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 184 [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, 185 [PCIE2] = SLOT_PCIE3 }, 186 [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, 187 [PCIE2] = SLOT_PCIE3, 188 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 189 [0x1c] = { [PCIE1] = SLOT_PCIE1, 190 [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, 191 [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, 192 [0x1f] = { [PCIE1] = SLOT_PCIE1 }, 193 }; 194 195 196 /* 197 * Returns the name of the slot to which the PCIe or SATA controller is 198 * connected 199 */ 200 const char *board_serdes_name(enum srds_prtcl device) 201 { 202 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 203 u32 pordevsr = in_be32(&gur->pordevsr); 204 unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 205 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 206 enum slot_id slot = serdes_dev_slot[srds_cfg][device]; 207 const char *name = slot_names[slot]; 208 209 if (name) 210 return name; 211 else 212 return "Nothing"; 213 } 214 215 void hw_watchdog_reset(void) 216 { 217 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); 218 219 clrbits_be32(&pgpio->gpdat, 0x00000400); 220 setbits_be32(&pgpio->gpdat, 0x00000400); 221 } 222 223 #ifdef CONFIG_TRAILBLAZER 224 int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 225 { 226 return run_command(env_get("bootcmd"), flag); 227 } 228 229 int board_early_init_r(void) 230 { 231 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); 232 233 /* 234 * GPIO3_12 PPC_SYSTEMREADY# 235 */ 236 setbits_be32(&pgpio->gpdir, 0x00080000); 237 setbits_be32(&pgpio->gpodr, 0x00080000); 238 clrbits_be32(&pgpio->gpdat, 0x00080000); 239 240 return ccdm_compute_self_hash(); 241 } 242 243 int last_stage_init(void) 244 { 245 startup_ccdm_id_module(); 246 return 0; 247 } 248 249 #else 250 void pci_init_board(void) 251 { 252 fsl_pcie_init_board(0); 253 254 hydra_initialize(); 255 } 256 257 int board_early_init_r(void) 258 { 259 unsigned int k = 0; 260 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR); 261 262 /* wait for FPGA configuration to finish */ 263 while (!pca9698_get_value(0x22, 11) && (k++ < 30)) 264 udelay(100000); 265 266 if (k > 30) { 267 puts("FPGA configuration timed out.\n"); 268 } else { 269 /* clear FPGA reset */ 270 udelay(1000); 271 setbits_be32(&pgpio->gpdat, 0x00100000); 272 } 273 274 /* give time for PCIe link training */ 275 udelay(100000); 276 277 /* 278 * GPIO3_12 PPC_SYSTEMREADY# 279 */ 280 setbits_be32(&pgpio->gpdir, 0x00080000); 281 setbits_be32(&pgpio->gpodr, 0x00080000); 282 clrbits_be32(&pgpio->gpdat, 0x00080000); 283 284 return 0; 285 } 286 287 int last_stage_init(void) 288 { 289 /* Turn on Parade DP501 */ 290 pca9698_direction_output(0x22, 7, 1); 291 udelay(500000); 292 293 dp501_powerup(0x08); 294 295 startup_ccdm_id_module(); 296 297 return 0; 298 } 299 300 /* 301 * Initialize on-board and/or PCI Ethernet devices 302 * 303 * Returns: 304 * <0, error 305 * 0, no ethernet devices found 306 * >0, number of ethernet devices initialized 307 */ 308 int board_eth_init(bd_t *bis) 309 { 310 struct fsl_pq_mdio_info mdio_info; 311 struct tsec_info_struct tsec_info[2]; 312 unsigned int num = 0; 313 314 #ifdef CONFIG_TSEC1 315 SET_STD_TSEC_INFO(tsec_info[num], 1); 316 num++; 317 #endif 318 #ifdef CONFIG_TSEC2 319 SET_STD_TSEC_INFO(tsec_info[num], 2); 320 num++; 321 #endif 322 323 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 324 mdio_info.name = DEFAULT_MII_NAME; 325 fsl_pq_mdio_init(bis, &mdio_info); 326 327 return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); 328 } 329 330 #ifdef CONFIG_OF_BOARD_SETUP 331 int ft_board_setup(void *blob, bd_t *bd) 332 { 333 phys_addr_t base; 334 phys_size_t size; 335 336 ft_cpu_setup(blob, bd); 337 338 base = env_get_bootm_low(); 339 size = env_get_bootm_size(); 340 341 fdt_fixup_memory(blob, (u64)base, (u64)size); 342 343 #ifdef CONFIG_HAS_FSL_DR_USB 344 fsl_fdt_fixup_dr_usb(blob, bd); 345 #endif 346 347 FT_FSL_PCI_SETUP; 348 349 return 0; 350 } 351 #endif 352 353 static void hydra_initialize(void) 354 { 355 unsigned int i; 356 pci_dev_t devno; 357 358 /* Find and probe all the matching PCI devices */ 359 for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) { 360 u32 val; 361 struct ihs_fpga *fpga; 362 u32 versions; 363 u32 fpga_version; 364 u32 fpga_features; 365 366 unsigned hardware_version; 367 unsigned feature_uart_channels; 368 unsigned feature_sb_channels; 369 370 /* Try to enable I/O accesses and bus-mastering */ 371 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 372 pci_write_config_dword(devno, PCI_COMMAND, val); 373 374 /* Make sure it worked */ 375 pci_read_config_dword(devno, PCI_COMMAND, &val); 376 if (!(val & PCI_COMMAND_MEMORY)) { 377 puts("Can't enable I/O memory\n"); 378 continue; 379 } 380 if (!(val & PCI_COMMAND_MASTER)) { 381 puts("Can't enable bus-mastering\n"); 382 continue; 383 } 384 385 /* read FPGA details */ 386 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, 387 PCI_REGION_MEM); 388 389 /* disable sideband clocks */ 390 writel(1, &fpga->control); 391 392 versions = readl(&fpga->versions); 393 fpga_version = readl(&fpga->fpga_version); 394 fpga_features = readl(&fpga->fpga_features); 395 396 hardware_version = versions & 0xf; 397 feature_uart_channels = (fpga_features >> 6) & 0x1f; 398 feature_sb_channels = fpga_features & 0x1f; 399 400 printf("FPGA%d: ", i); 401 402 switch (hardware_version) { 403 case HWVER_100: 404 printf("HW-Ver 1.00\n"); 405 break; 406 407 case HWVER_110: 408 printf("HW-Ver 1.10\n"); 409 break; 410 411 case HWVER_120: 412 printf("HW-Ver 1.20\n"); 413 break; 414 415 default: 416 printf("HW-Ver %d(not supported)\n", 417 hardware_version); 418 break; 419 } 420 421 printf(" FPGA V %d.%02d, features:", 422 fpga_version / 100, fpga_version % 100); 423 424 printf(" %d uart channel(s)", feature_uart_channels); 425 printf(" %d sideband channel(s)\n", feature_sb_channels); 426 } 427 } 428 #endif 429